Parallel geostatistics for sparse and dense datasets

Very large spatially-referenced datasets, for example, those derived from satellite-based sensors which sample across the globe or large monitoring networks of individual sensors, are becoming increasingly common and more widely available for use in environmental decision making. In large or dense sensor networks, huge quantities of data can be collected over small time periods. In many applications the generation of maps, or predictions at specific locations, from the data in (near) real-time is crucial. Geostatistical operations such as interpolation are vital in this map-generation process and in emergency situations, the resulting predictions need to be available almost instantly, so that decision makers can make informed decisions and define risk and evacuation zones. It is also helpful when analysing data in less time critical applications, for example when interacting directly with the data for exploratory analysis, that the algorithms are responsive within a reasonable time frame. Performing geostatistical analysis on such large spatial datasets can present a number of problems, particularly in the case where maximum likelihood. Although the storage requirements only scale linearly with the number of observations in the dataset, the computational complexity in terms of memory and speed, scale quadratically and cubically respectively. Most modern commodity hardware has at least 2 processor cores if not more. Other mechanisms for allowing parallel computation such as Grid based systems are also becoming increasingly commonly available. However, currently there seems to be little interest in exploiting this extra processing power within the context of geostatistics. In this paper we review the existing parallel approaches for geostatistics. By recognising that diffeerent natural parallelisms exist and can be exploited depending on whether the dataset is sparsely or densely sampled with respect to the range of variation, we introduce two contrasting novel implementations of parallel algorithms based on approximating the data likelihood extending the methods of Vecchia [1988] and Tresp [2000]. Using parallel maximum likelihood variogram estimation and parallel prediction algorithms we show that computational time can be significantly reduced. We demonstrate this with both sparsely sampled data and densely sampled data on a variety of architectures ranging from the common dual core processor, found in many modern desktop computers, to large multi-node super computers. To highlight the strengths and weaknesses of the diffeerent methods we employ synthetic data sets and go on to show how the methods allow maximum likelihood based inference on the exhaustive Walker Lake data set.

The design and implementation of a portable operating system for microcomputers

Communication and portability are the two main problems facing the user. An operating system, called PORTOS, was developed to solve these problems for users on dedicated microcomputer systems. Firstly, an interface language was defined, according to the anticipated requirements and behaviour of its potential users. Secondly, the PORTOS operating system was developed as a processor for this language. The system is currently running on two minicomputers of highly different architectures. PORTOS achieves its portability through its high-level design, and implementation in CORAL66. The interface language consists of a set of user cotnmands and system responses. Although only a subset has been implemented, owing to time and manpower constraints, promising results were achieved regarding the usability of the language, and its portability.

Improved design of all-optical processor for modular arithmetic

A new improved design of an all-optical processor that performs modular arithmetic is presented. The modulo-processor is based on all-optical circuit of interconnected semiconductor optical amplifier logic gates. The design allows processing times of less than 1 µs for 16-bit operation at 10 Gb/s and up to 32-bit operation at 100 Gb/s.

Energy efficient architectures and techniques for green radio access networks

Energy consumption in wireless networks, and in particular in cellular mobile networks, is now of major concern in respect of their potential adverse impact upon the environment and their escalating operating energy costs. The recent phenomenal growth of data services in cellular mobile networks has exacerbated the energy consumption issue and is forcing researchers to address how to design future wireless networks that take into account energy consumption constraints. One fundamental approach to reduce energy consumption of wireless networks is to adopt new radio access architectures and radio techniques. The Mobile VCE (MVCE) Green Radio project, established in 2009, is considering such new architectural and technical approaches. This paper reports highlights the key research issues pursued in the MVCE Green Radio project.

Energy efficient radio access architectures for green radio:large versus small cell size deployment

In this paper new architectural approaches that improve the energy efficiency of a cellular radio access network (RAN) are investigated. The aim of the paper is to characterize both the energy consumption ratio (ECR) and the energy consumption gain (ECG) of a cellular RAN when the cell size is reduced for a given user density and service area. The paper affirms that reducing the cell size reduces the cell ECR as desired while increasing the capacity density but the overall RAN energy consumption remains unchanged. In order to trade the increase in capacity density with RAN energy consumption, without degrading the cell capacity provision, a sleep mode is introduced. In sleep mode, cells without active users are powered-off, thereby saving energy. By combining a sleep mode with a small-cell deployment architecture, the paper shows that the ECG can be increased by the factor n = (R/R) while the cell ECR continues to decrease with decreasing cell size.

Facile route to conformal hydrotalcite coatings over complex architectures:a hierarchically ordered nanoporous base catalyst for FAME production

An alkali- and nitrate-free hydrotalcite coating has been grafted onto the surface of a hierarchically ordered macroporous-mesoporous SBA-15 template via stepwise growth of conformal alumina adlayers and their subsequent reaction with magnesium methoxide. The resulting low dimensional hydrotalcite crystallites exhibit excellent per site activity for the base catalysed transesterification of glyceryl triolein with methanol for FAME production.

Governance architectures for inter-organisational R&D collaboration

Inter-organizational relationships are becoming an increasingly important source of competitive advantage and innovation. This study looks at these relationships in the context of inter-organizational R&D collaborations in the European automotive industry. Previous work led to the proposal of a competence-based portfolio framework that explains the design of the inter-organizational architecture and an indicative relationship strategy. This framework comprises four distinct types of governance architecture and relationship strategy. This paper reports on the first confirmatory transfer study, conducted at Jaguar Land Rover, in the UK. The study illustrates developmental paths and patterns in the evolution of inter-organizational relationships using empirical insights. Their configuration and dynamic evolution is contingent upon the ‘engageability’ of the partner companies’ competences based on their attractiveness, transferability and maturity. The study shows that the contingency framework is transferable and practically useful, as well as yielding further practical narrative about inter-organizational practice.

Design of a multi-processor control systems

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Design and analysis of an all-optical processor for modular arithmetic

We present a logical design of an all-optical processor that performs modular arithmetic. The overall design is based a set of interconnected modules that use all-optical gates to perform simple logical functions. The all-optical logic gates are based on the semiconductor optical amplifier nonlinear loop. Simulation results are presented and some practical design issues are discussed.

Design of fast core node processor for packet forwarding without header modification in optical networks

We present a design of a fast all-optical core-node processor that performs packet-forwarding in optical networks without header-modification. The design is based on bit-serial architecture using TOADs as logic-gates that perform modulo-arithmetic to forward packets.