Topological changes in 2D simplicial meshes for the simulation of fractures

A method for the introduction of strong discontinuities into a mesh will be developed. This method, applicable to a number of eXtended Finite Element Methods (XFEM) with intra-element strong discontinuities will be demonstrated with one specific method: the Generalized Cohesive Element (GCE) method. The algorithm utilizes a subgraph mesh representation which may insert the GCE either adaptively during the course of the analysis or a priori. Using this subgraphing algorithm, the insertion time is O(n) to the number of insertions. Numerical examples are presented demonstrating the advantages of the subgraph insertion method.

First-principles studies of boron nanostructures

Boron is an 'electron deficient' element which has a rather fascinating chemical versatility. In the solid state, the elemental boron has neither a pure covalent nor a pure metallic character. As a result, its vast structural dimensionally and peculiar bonding features hold a unique place among other elements in the periodic table. In order to understand and properly describe these unusual bonding features, a detailed and systematic theoretical study is needed. In this work, I will show that some of the qualitative features of boron nanostructures, including clusters, sheets and nanotubes can easily be extracted from the results of first principles calculations based on density functional theory. Specifically, the size-dependent evolution of topological structures and bonding characteristics of boron clusters, Bn will be discussed. Based on the scenario observed in the boron clusters, the unique properties of boron sheets and boron nanotubes will be described. Moreover, the ballistic electron transport in single-walled carbon nanotubes will be considered. It is expected that the theoretical results obtained in the present thesis will initiate further studies on boron nanostructures, which will be helpful in understanding, designing and realizing boron-based nanoscale devices.

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling.