RF-sputter fabrication of magnetic garnet thin films and simulation modeling for 1-D magnetic photonic crystal waveguide devices

One dimensional magnetic photonic crystals (1D-MPC) are promising structures for integrated optical isolator applications. Rare earth substituted garnet thin films with proper Faraday rotation are required to fabricate planar 1D-MPCs. In this thesis, flat-top response 1D-MPC was proposed and spectral responses and Faraday rotation were modeled. Bismuth substituted iron garnet films were fabricated by RF magnetron sputtering and structures, compositions, birefringence and magnetooptical properties were studied. Double layer structures for single mode propagation were also fabricated by sputtering for the first time. Multilayer stacks with multiple defects (phase shift) composed of Ce-YIG and GGG quarter-wave plates were simulated by the transfer matrix method. The transmission and Faraday rotation characteristics were theoretically studied. It is found that flat-top response, with 100% transmission and near 45o rotation is achievable by adjusting the inter-defect spacing, for film structures as thin as 30 to 35 μm. This is better than 3-fold reduction in length compared to the best Ce-YIG films for comparable rotations, thus allows a considerable reduction in size in manufactured optical isolators. Transmission bands as wide as 7nm were predicted, which is considerable improvement over 2 defects structure. Effect of repetition number and ratio factor on transmission and Faraday rotation ripple factors for the case of 3 and 4 defects structure has been discussed. Diffraction across the structure corresponds to a longer optical path length. Thus the use of guided optics is required to minimize the insertion losses in integrated devices. This part is discussed in chapter 2 in this thesis. Bismuth substituted iron garnet thin films were prepared by RF magnetron sputtering. We investigated or measured the deposition parameters optimization, crystallinity, surface morphologies, composition, magnetic and magnetooptical properties. A very high crystalline quality garnet film with smooth surface has been heteroepitaxially grown on (111) GGG substrate for films less than 1μm. Dual layer structures with two distinct XRD peaks (within a single sputtered film) start to develop when films exceed this thickness. The development of dual layer structure was explained by compositional gradient across film thickness, rather than strain gradient proposed by other authors. Lower DC self bias or higher substrate temperature is found to help to delay the appearance of the 2nd layer. The deposited films show in-plane magnetization, which is advantageous for waveguide devices application. Propagation losses of fabricated waveguides can be decreased by annealing in an oxygen atmosphere from 25dB/cm to 10dB/cm. The Faraday rotation at λ=1.55μm were also measured for the waveguides. FR is small (10° for a 3mm long waveguide), due to the presence of linear birefringence. This part is covered in chapter 4. We also investigated the elimination of linear birefringence by thickness tuning method for our sputtered films. We examined the compressively and tensilely strained films and analyze the photoelastic response of the sputter deposited garnet films. It has been found that the net birefringence can be eliminated under planar compressive strain conditions by sputtering. Bi-layer GGG on garnet thin film yields a reduced birefringence. Temperature control during the sputter deposition of GGG cover layer is critical and strongly influences the magnetization and birefringence level in the waveguide. High temperature deposition lowers the magnetization and increases the linear birefringence in the garnet films. Double layer single mode structures fabricated by sputtering were also studied. The double layer, which shows an in-plane magnetization, has an increased RMS roughness upon upper layer deposition. The single mode characteristic was confirmed by prism coupler measurement. This part is discussed in chapter 5.

Optical Waveguides and Structures for Short Haul Optical Communication Channels within Printed Circuit Boards

Optical waveguides have shown promising results for use within printed circuit boards. These optical waveguides have higher bandwidth than traditional copper transmission systems and are immune to electromagnetic interference. Design parameters for these optical waveguides are needed to ensure an optimal link budget. Modeling and simulation methods are used to determine the optimal design parameters needed in designing the waveguides. As a result, optical structures necessary for incorporating optical waveguides into printed circuit boards are designed and optimized. Embedded siloxane polymer waveguides are investigated for their use in optical printed circuit boards. This material was chosen because it has low absorption, high temperature stability, and can be deposited using common processing techniques. Two sizes of waveguides are investigated, 50 $unit{mu m}$ multimode and 4 - 9 $unit{mu m}$ single mode waveguides. A beam propagation method is developed for simulating the multimode and single mode waveguide parameters. The attenuation of simulated multimode waveguides are able to match the attenuation of fabricated waveguides with a root mean square error of 0.192 dB. Using the same process as the multimode waveguides, parameters needed to ensure a low link loss are found for single mode waveguides including maximum size, minimum cladding thickness, minimum waveguide separation, and minimum bend radius. To couple light out-of-plane to a transmitter or receiver, a structure such as a vertical interconnect assembly (VIA) is required. For multimode waveguides the optimal placement of a total internal reflection mirror can be found without prior knowledge of the waveguide length. The optimal placement is found to be either 60 µm or 150 µm away from the end of the waveguide depending on which metric a designer wants to optimize the average output power, the output power variance, or the maximum possible power loss. For single mode waveguides a volume grating coupler is designed to couple light from a silicon waveguide to a polymer single mode waveguide. A focusing grating coupler is compared to a perpendicular grating coupler that is focused by a micro-molded lens. The focusing grating coupler had an optical loss of over -14 dB, while the grating coupler with a lens had an optical loss of -6.26 dB.

EVALUATION OF POTENTIAL TRANSLOAD FACILITY LOCATIONS IN THE UPPER PENINSULA (UP) OF MICHIGAN

Shippers want to improve their transportation efficiency and rail transportation has the potential to provide an economical alternative to trucking, but it also has potential drawbacks. The pressure to optimize transportation supply chain logistics has resulted in growing interest in multimodal alternatives, such as a combination of truck and rail transportation, but the comparison of multimodal and modal alternatives can be complicated. Shippers in Michigan’s Upper Peninsula (UP) face similar challenges. Adding to the challenge is the distance from major markets and the absence of available facilities for transloading activities. This study reviewed three potential locations for a transload facility (Nestoria, Ishpeming, and Amasa) where truck shipments could be transferred to rail and vice versa. These locations were evaluated on the basis of transportation costs for shippers when compared to the use of single mode transportation by truck to Wisconsin, Chicago, Minneapolis, and Sault Ste. Marie. In addition to shipping costs, the study also evaluated the potential impact of future carbon emission penalties on the shipping cost and the effects of changing fuel prices on shipping cost. The study used data obtained from TRANSEARCH database (2009) and found that although there were slight differences between percent savings for the three locations, any of them could provide potential benefits for movements to Chicago and Minneapolis, as long as final destination could be accessed by rail for delivery. Short haul movements of less than 200 miles (Wisconsin and Sault Ste. Marie) were not cost effective for multimodal transport. The study also found that for every dollar increase in fuel price, cost savings from multimodal option increased by three to five percent, but the inclusion of emission costs would only add one to two percent additional savings. Under a specific case study that addressed shipments by Northern Hardwoods, the most distant locations in Wisconsin would also provide cost savings, partially due to the possibility of using Michigan trucks with higher carrying capacity for the initial movement from the facility to transload location. In addition, Minneapolis movements were found to provide savings for Northern Hardwoods, even without final rail access.

Direct Write Fabrication of Waveguides and Interconnects for Optical Printed Wiring Boards

Current copper based circuit technology is becoming a limiting factor in high speed data transfer applications as processors are improving at a faster rate than are developments to increase on board data transfer. One solution is to utilize optical waveguide technology to overcome these bandwidth and loss restrictions. The use of this technology virtually eliminates the heat and cross-talk loss seen in copper circuitry, while also operating at a higher bandwidth. Transitioning current fabrication techniques from small scale laboratory environments to large scale manufacturing presents significant challenges. Optical-to-electrical connections and out-of-plane coupling are significant hurdles in the advancement of optical interconnects. The main goals of this research are the development of direct write material deposition and patterning tools for the fabrication of waveguide systems on large substrates, and the development of out-of-plane coupler components compatible with standard fiber optic cabling. Combining these elements with standard printed circuit boards allows for the fabrication of fully functional optical-electrical-printed-wiring-boards (OEPWBs). A direct dispense tool was designed, assembled, and characterized for the repeatable dispensing of blanket waveguide layers over a range of thicknesses (25-225 µm), eliminating waste material and affording the ability to utilize large substrates. This tool was used to directly dispense multimode waveguide cores which required no UV definition or development. These cores had circular cross sections and were comparable in optical performance to lithographically fabricated square waveguides. Laser direct writing is a non-contact process that allows for the dynamic UV patterning of waveguide material on large substrates, eliminating the need for high resolution masks. A laser direct write tool was designed, assembled, and characterized for direct write patterning waveguides that were comparable in quality to those produced using standard lithographic practices (0.047 dB/cm loss for laser written waveguides compared to 0.043 dB/cm for lithographic waveguides). Straight waveguides, and waveguide turns were patterned at multimode and single mode sizes, and the process was characterized and documented. Support structures such as angled reflectors and vertical posts were produced, showing the versatility of the laser direct write tool. Commercially available components were implanted into the optical layer for out-of-plane routing of the optical signals. These devices featured spherical lenses on the input and output sides of a total internal reflection (TIR) mirror, as well as alignment pins compatible with standard MT design. Fully functional OEPWBs were fabricated featuring input and output out-of-plane optical signal routing with total optical losses not exceeding 10 dB. These prototypes survived thermal cycling (-40°C to 85°C) and humidity exposure (95±4% humidity), showing minimal degradation in optical performance. Operational failure occurred after environmental aging life testing at 110°C for 216 hours.

Fabrication and characterization of room temperature operating single electron transistors using focused ion beam technologies

The single electron transistor (SET) is a Coulomb blockade device, whose operation is based on the controlled manipulation of individual electrons. Single electron transistors show immense potential to be used in future ultra lowpower devices, high density memory and also in high precision electrometry. Most SET devices operate at cryogenic temperatures, because the charging energy is much smaller than the thermal oscillations. The room temperature operation of these devices is possible with sub- 10nm nano-islands due to the inverse dependance of charging energy on the radius of the conducting nano-island. The fabrication of sub-10nm features with existing lithographic techniques is a technological challenge. Here we present the results for the first room temperature operating SET device fabricated using Focused Ion Beam deposition technology. The SET device, incorporates an array of tungsten nano-islands with an average diameter of 8nm. The SET devices shows clear Coulomb blockade for different gate voltages at room temperature. The charging energy of the device was calculated to be 160.0 meV; the capacitance per junction was found to be 0.94 atto F; and the tunnel resistance per junction was calculated to be 1.26 G Ω. The tunnel resistance is five orders of magnitude larger than the quantum of resistance (26 k Ω) and allows for the localization of electrons on the tungsten nano-island. The lower capacitance of the device combined with the high tunnel resistance, allows for the Coulomb blockade effects observed at room temperature. Different device configurations, minimizing the total capacitance of the device have been explored. The effect of the geometry of the nano electrodes on the device characteristics has been presented. Simulated device characteristics, based on the soliton model have been discussed. The first application of SET device as a gas sensor has been demonstrated.

Model to describe the mode I fracture of steel fiber reinforced ultra-high performance concrete

Ultra-high performance fiber reinforced concrete (UHPFRC) has arisen from the implementation of a variety of concrete engineering and materials science concepts developed over the last century. This material offers superior strength, serviceability, and durability over its conventional counterparts. One of the most important differences for UHPFRC over other concrete materials is its ability to resist fracture through the use of randomly dispersed discontinuous fibers and improvements to the fiber-matrix bond. Of particular interest is the materials ability to achieve higher loads after first crack, as well as its high fracture toughness. In this research, a study of the fracture behavior of UHPFRC with steel fibers was conducted to look at the effect of several parameters related to the fracture behavior and to develop a fracture model based on a non-linear curve fit of the data. To determine this, a series of three-point bending tests were performed on various single edge notched prisms (SENPs). Compression tests were also performed for quality assurance. Testing was conducted on specimens of different cross-sections, span/depth (S/D) ratios, curing regimes, ages, and fiber contents. By comparing the results from prisms of different sizes this study examines the weakening mechanism due to the size effect. Furthermore, by employing the concept of fracture energy it was possible to obtain a comparison of the fracture toughness and ductility. The model was determined based on a fit to P-w fracture curves, which was cross referenced for comparability to the results. Once obtained the model was then compared to the models proposed by the AFGC in the 2003 and to the ACI 544 model for conventional fiber reinforced concretes.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling.

STOCHASTIC CHARGE TRANSPORT IN MULTI-ISLAND SINGLE-ELECTRON TUNNELING DEVICES

The physics of the operation of singe-electron tunneling devices (SEDs) and singe-electron tunneling transistors (SETs), especially of those with multiple nanometer-sized islands, has remained poorly understood in spite of some intensive experimental and theoretical research. This computational study examines the current-voltage (IV) characteristics of multi-island single-electron devices using a newly developed multi-island transport simulator (MITS) that is based on semi-classical tunneling theory and kinetic Monte Carlo simulation. The dependence of device characteristics on physical device parameters is explored, and the physical mechanisms that lead to the Coulomb blockade (CB) and Coulomb staircase (CS) characteristics are proposed. Simulations using MITS demonstrate that the overall IV characteristics in a device with a random distribution of islands are a result of a complex interplay among those factors that affect the tunneling rates that are fixed a priori (e.g. island sizes, island separations, temperature, gate bias, etc.), and the evolving charge state of the system, which changes as the source-drain bias (VSD) is changed. With increasing VSD, a multi-island device has to overcome multiple discrete energy barriers (up-steps) before it reaches the threshold voltage (Vth). Beyond Vth, current flow is rate-limited by slow junctions, which leads to the CS structures in the IV characteristic. Each step in the CS is characterized by a unique distribution of island charges with an associated distribution of tunneling probabilities. MITS simulation studies done on one-dimensional (1D) disordered chains show that longer chains are better suited for switching applications as Vth increases with increasing chain length. They are also able to retain CS structures at higher temperatures better than shorter chains. In sufficiently disordered 2D systems, we demonstrate that there may exist a dominant conducting path (DCP) for conduction, which makes the 2D device behave as a quasi-1D device. The existence of a DCP is sensitive to the device structure, but is robust with respect to changes in temperature, gate bias, and VSD. A side gate in 1D and 2D systems can effectively control Vth. We argue that devices with smaller island sizes and narrower junctions may be better suited for practical applications, especially at room temperature.