Fabrication of nanoparticles by short-distance sputter deposition

During the past decades, tremendous research interests have been attracted to investigate nanoparticles due to their promising catalytic, magnetic, and optical properties. In this thesis, two novel methods of nanoparticle fabrication were introduced and the basic formation mechanisms were studied. Metal nanoparticles and polyurethane nanoparticles were separately fabricated by a short-distance sputter deposition technique and a reactive ion etching process. First, a sputter deposition method with a very short target-substrate distance is found to be able to generate metal nanoparticles on the glass substrate inside a RIE chamber. The distribution and morphology of nanoparticles are affected by the distance, the ion concentration and the process time. Densely-distributed nanoparticles of various compositions are deposited on the substrate surface when the target-substrate distance is smaller than 130mm. It is much less than the atoms’ mean free path, which is the threshold in previous research for nanoparticles’ formation. Island structures are formed when the distance is increased to 510mm, indicating the tendency to form continuous thin film. The trend is different from previously-reported sputtering method for nanoparticle fabrication, where longer distance between the target and the substrate facilitates the formation of nanoparticle. A mechanism based on the seeding effect of the substrate is proposed to interpret the experimental results. Secondly, in polyurethane nanoparticles’ fabrication, a mechanism is put forward based on the microphase separation phenomenon in block copolymer thin film. The synthesized polymers have formed dispersed and continuous phases because of the different properties between segments. With harder mechanical property, the dispersed phase is remained after RIE process while the continuous phase is etched away, leading to the formation of nanoparticles on the substrate. The nanoparticles distribution is found to be affected by the heating effect, the process time and the plasma power. Superhydrophilic property is found on samples with these two types of nanoparticles. The relationship between the nanostructure and the hydrophilicity is studied for further potential applications.

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling.