Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

As the performance gap between microprocessors and memory continues to increase, main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant localities and SDRAM devices provide parallelism through multiple banks and channels. These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency. The proposed bit-reversal address mapping attempts to distribute main memory accesses evenly in the SDRAM address space to enable bank parallelism. As memory accesses to unique banks are interleaved, the access latencies are partially hidden and therefore reduced. With the consideration of cache conflict misses, bit-reversal address mapping is able to direct potential row conflicts to different banks, further improving the performance. The proposed burst scheduling is a novel access reordering mechanism, which creates bursts by clustering accesses directed to the same rows of the same banks. Subjected to a threshold, reads are allowed to preempt writes and qualified writes are piggybacked at the end of the bursts. A sophisticated access scheduler selects accesses based on priorities and interleaves accesses to maximize the SDRAM data bus utilization. Consequentially burst scheduling reduces row conflict rate, increasing and exploiting the available row locality. Using a revised SimpleScalar and M5 simulator, both techniques are evaluated and compared with existing academic and industrial solutions. With SPEC CPU2000 benchmarks, bit-reversal reduces the execution time by 14% on average over traditional page interleaving address mapping. Burst scheduling also achieves a 15% reduction in execution time over conventional bank in order scheduling. Working constructively together, bit-reversal and burst scheduling successfully achieve a 19% speedup across simulated benchmarks.

Climatological study of transport to the PICO-NARE site using atmospheric backward trajectories

This study developed a transport climatology to the PICO-NARE station, in the central North Atlantic Ocean, using a 40-year set of atmospheric back trajectories. The trajectory set was subjected to a cluster analysis in order to group trajectories into six flow patterns, or clusters. An air flow probability analysis was conducted in conjunction with the cluster analysis in order to determine the source regions for flow to the site. Seasonal differences in the flow patterns were found, which included enhanced westerly flow in the winter, decreased westerly flow in the summer, and spring and fall having moderate westerly flow. The North Atlantic Oscillation had a significant impact on the winter and fall seasons and less significant impacts during spring and summer. The results of the climatology can be used in conjunction with measurements of ozone, CO, NOx, and NOy, which are currently being measured at the site, to develop a long-term, seasonal climatology of transport of pollutants to the central North Atlantic.