Evaluating stress patterns for Plio-Quaternary brittle deformation along the Calama-Olacapato-El Toro fault zone, Central Andes

Understanding the geometry and kinematics of the major structures of an orogen is important to elucidate its style of deformation, as well as its tectonic evolution. We describe the temporal and spatial changes in the state of stress of the trans-orogen area of the Calama-Olacapato-El Toro (COT) Fault Zone in the Central Andes, at about 24°S within the northern portion of the Puna Plateau between the Argentina-Chile border. The importance of the COT derives principally from the Quaternary-Holocene activity recognized on some segments, which may shed new light on its possible control on Quaternary volcanism and on the seismic hazard evaluation of the area. Field geological surveys along with kinematic analysis and numerical inversion of ∼140 new fault-slip measurements have revealed that this portion of the COT zone, previously considered a continuous, long-lived lineament, in reality has been subjected to three different kinematic regimes: 1) a Miocene transpressional phase with the maximum principal stress (σ1) chiefly trending NNE-SSW; 2) an extensional phase that started by 9 Ma, with a horizontal NW-SE-striking minimum principal stress (σ3) – permutations between σ2 and σ3 axes have been recognized at two sites – and 3) a left-lateral strike-slip phase with a horizontal ∼E-W &sigma1 and ∼N-S σ3 dating to the Late Pliocene-Quaternary. Spatially, in the Quaternary, the left-lateral component decreases toward the westernmost tip of the COT, where it transitions to extension; this produced to a N-S horst and graben structure. Hence, even if transcurrence is still active in the eastern portion of the COT, as focal mechanisms of crustal earthquakes indicate, our study demonstrates that extension is becoming the predominant structural style of deformation, at least in the western region. These major temporal and spatial changes in the tectonic regimes are attributed in part to changes in the magnitude of the boundary forces due to subduction processes. The overall orogen-perpendicular extension might be the result of vertical stress larger than both the horizontal stresses induced by gravitational effect of a thickened crust.

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling.