Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

As the performance gap between microprocessors and memory continues to increase, main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant localities and SDRAM devices provide parallelism through multiple banks and channels. These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency. The proposed bit-reversal address mapping attempts to distribute main memory accesses evenly in the SDRAM address space to enable bank parallelism. As memory accesses to unique banks are interleaved, the access latencies are partially hidden and therefore reduced. With the consideration of cache conflict misses, bit-reversal address mapping is able to direct potential row conflicts to different banks, further improving the performance. The proposed burst scheduling is a novel access reordering mechanism, which creates bursts by clustering accesses directed to the same rows of the same banks. Subjected to a threshold, reads are allowed to preempt writes and qualified writes are piggybacked at the end of the bursts. A sophisticated access scheduler selects accesses based on priorities and interleaves accesses to maximize the SDRAM data bus utilization. Consequentially burst scheduling reduces row conflict rate, increasing and exploiting the available row locality. Using a revised SimpleScalar and M5 simulator, both techniques are evaluated and compared with existing academic and industrial solutions. With SPEC CPU2000 benchmarks, bit-reversal reduces the execution time by 14% on average over traditional page interleaving address mapping. Burst scheduling also achieves a 15% reduction in execution time over conventional bank in order scheduling. Working constructively together, bit-reversal and burst scheduling successfully achieve a 19% speedup across simulated benchmarks.

Evaluation of factors affecting speed perception in a driving simulator

The present study was conducted to determine the effects of different variables on the perception of vehicle speeds in a driving simulator. The motivations of the study include validation of the Michigan Technological University Human Factors and Systems Lab driving simulator, obtaining a better understanding of what influences speed perception in a virtual environment, and how to improve speed perception in future simulations involving driver performance measures. Using a fixed base driving simulator, two experiments were conducted, the first to evaluate the effects of subject gender, roadway orientation, field of view, barriers along the roadway, opposing traffic speed, and subject speed judgment strategies on speed estimation, and the second to evaluate all of these variables as well as feedback training through use of the speedometer during a practice run. A mixed procedure model (mixed model ANOVA) in SAS® 9.2 was used to determine the significance of these variables in relation to subject speed estimates, as there were both between and within subject variables analyzed. It was found that subject gender, roadway orientation, feedback training, and the type of judgment strategy all significantly affect speed perception. By using curved roadways, feedback training, and speed judgment strategies including road lines, speed limit experience, and feedback training, speed perception in a driving simulator was found to be significantly improved.