Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

As the performance gap between microprocessors and memory continues to increase, main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant localities and SDRAM devices provide parallelism through multiple banks and channels. These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency. The proposed bit-reversal address mapping attempts to distribute main memory accesses evenly in the SDRAM address space to enable bank parallelism. As memory accesses to unique banks are interleaved, the access latencies are partially hidden and therefore reduced. With the consideration of cache conflict misses, bit-reversal address mapping is able to direct potential row conflicts to different banks, further improving the performance. The proposed burst scheduling is a novel access reordering mechanism, which creates bursts by clustering accesses directed to the same rows of the same banks. Subjected to a threshold, reads are allowed to preempt writes and qualified writes are piggybacked at the end of the bursts. A sophisticated access scheduler selects accesses based on priorities and interleaves accesses to maximize the SDRAM data bus utilization. Consequentially burst scheduling reduces row conflict rate, increasing and exploiting the available row locality. Using a revised SimpleScalar and M5 simulator, both techniques are evaluated and compared with existing academic and industrial solutions. With SPEC CPU2000 benchmarks, bit-reversal reduces the execution time by 14% on average over traditional page interleaving address mapping. Burst scheduling also achieves a 15% reduction in execution time over conventional bank in order scheduling. Working constructively together, bit-reversal and burst scheduling successfully achieve a 19% speedup across simulated benchmarks.

SPRING DISCHARGE MONITORING IN LOW-RESOURCE SETTINGS: A CASE STUDY OF CONCEPCIÓN CHIQUIRICHAPA, GUATEMALA

Water springs are the principal source of water for many localities in Central America, including the municipality of Concepción Chiquirichapa in the Western Highlands of Guatemala. Long-term monitoring records are critical for informed water management as well as resource forecasting, though data are scarce and monitoring in low-resource settings presents special challenges. Spring discharge was monitored monthly in six municipal springs during the author’s Peace Corps assignment, from May 2011 to March 2012, and water level height was monitored in two spring boxes over the same time period using automated water-level loggers. The intention of this approach was to circumvent the need for frequent and time-intensive manual measurement by identifying a fixed relationship between discharge and water level. No such relationship was identified, but the water level record reveals that spring yield increased for four months following Tropical Depression 12E in October 2011. This suggests that the relationship between extreme precipitation events and long-term water spring yields in Concepción should be examined further. These limited discharge data also indicate that aquifer baseflow recession and catchment water balance could be successfully characterized if a long-term discharge record were established. This study also presents technical and social considerations for selecting a methodology for spring discharge measurement and highlights the importance of local interest in conducting successful community-based research in intercultural low-resource settings.