Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms

As the performance gap between microprocessors and memory continues to increase, main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant localities and SDRAM devices provide parallelism through multiple banks and channels. These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency. The proposed bit-reversal address mapping attempts to distribute main memory accesses evenly in the SDRAM address space to enable bank parallelism. As memory accesses to unique banks are interleaved, the access latencies are partially hidden and therefore reduced. With the consideration of cache conflict misses, bit-reversal address mapping is able to direct potential row conflicts to different banks, further improving the performance. The proposed burst scheduling is a novel access reordering mechanism, which creates bursts by clustering accesses directed to the same rows of the same banks. Subjected to a threshold, reads are allowed to preempt writes and qualified writes are piggybacked at the end of the bursts. A sophisticated access scheduler selects accesses based on priorities and interleaves accesses to maximize the SDRAM data bus utilization. Consequentially burst scheduling reduces row conflict rate, increasing and exploiting the available row locality. Using a revised SimpleScalar and M5 simulator, both techniques are evaluated and compared with existing academic and industrial solutions. With SPEC CPU2000 benchmarks, bit-reversal reduces the execution time by 14% on average over traditional page interleaving address mapping. Burst scheduling also achieves a 15% reduction in execution time over conventional bank in order scheduling. Working constructively together, bit-reversal and burst scheduling successfully achieve a 19% speedup across simulated benchmarks.

Keweenaw National Historical Park: Heritage Partnerships in an Industrial Landscape

This dissertation examines the genesis and development of Keweenaw National Historical Park in Michigan's Upper Peninsula. After the decline of a once-thriving copper mining industry, local residents pursued the creation of a national park as a way to encourage economic development, revitalize their community, and preserve their historic resources. Although they were ultimately successful in creating a national park, the park that was established was not the park that they envisioned. Over the next twenty years, the National Park Service, the park's federal Advisory Commission, and the communities on the Keweenaw Peninsula struggled to align unrealistic expectations with the actual capabilities and limitations of the park. The first chapter of this dissertation includes a short history of the decline of the copper industry in and around the village of Calumet, Michigan. This chapter also includes a discussion about the techniques and challenges of preserving and interpreting industrial heritage. Chapters 2 and 3 cover the events from the initial park proposal, to the expansion of the original idea, to the establishment of the park. Chapter 4 includes an examination of the enabling legislation and a discussion about the opportunities and challenges it provided. Chapters 5 through 8 cover the tenure of each of the four NPS superintendents as they navigated the complexities presented by a park model that was part partnership park and part traditional national park. Chapter 9 includes some key lessons, an assessment of the park's success, and some considerations for the future. In particular, Chapter 9 argues for an increased focus on the partnership aspects of the park, a reduction in the perceived scope of responsibilities, and a renewed effort to rally the existing partners in pursuing additional philanthropic support for the overall park.

Strategic Optimization Techniques For FRTU Deployment and Chip Physical Design

Combinatorial optimization is a complex engineering subject. Although formulation often depends on the nature of problems that differs from their setup, design, constraints, and implications, establishing a unifying framework is essential. This dissertation investigates the unique features of three important optimization problems that can span from small-scale design automation to large-scale power system planning: (1) Feeder remote terminal unit (FRTU) planning strategy by considering the cybersecurity of secondary distribution network in electrical distribution grid, (2) physical-level synthesis for microfluidic lab-on-a-chip, and (3) discrete gate sizing in very-large-scale integration (VLSI) circuit. First, an optimization technique by cross entropy is proposed to handle FRTU deployment in primary network considering cybersecurity of secondary distribution network. While it is constrained by monetary budget on the number of deployed FRTUs, the proposed algorithm identi?es pivotal locations of a distribution feeder to install the FRTUs in different time horizons. Then, multi-scale optimization techniques are proposed for digital micro?uidic lab-on-a-chip physical level synthesis. The proposed techniques handle the variation-aware lab-on-a-chip placement and routing co-design while satisfying all constraints, and considering contamination and defect. Last, the first fully polynomial time approximation scheme (FPTAS) is proposed for the delay driven discrete gate sizing problem, which explores the theoretical view since the existing works are heuristics with no performance guarantee. The intellectual contribution of the proposed methods establishes a novel paradigm bridging the gaps between professional communities.