Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design

To tackle the challenges at circuit level and system level VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the efficient solutions. At the circuit level, a new reliability-driven minimum cost Steiner routing and layer assignment scheme is proposed, and the first transceiver insertion algorithmic framework for the optical interconnect is proposed. At the system level, a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems, which optimizes system energy consumption under stochastic fault occurrences, is proposed. The embedded system design is also widely used in the smart home area for improving health, wellbeing and quality of life. The proposed scheduling scheme for multiprocessor embedded systems is hence extended to handle the energy consumption scheduling issues for smart homes. The extended scheme can arrange the household appliances for operation to minimize monetary expense of a customer based on the time-varying pricing model.

Study of and design procedure for dual circularly polarized waveguide slot arrays

For the past sixty years, waveguide slot radiator arrays have played a critical role in microwave radar and communication systems. They feature a well-characterized antenna element capable of direct integration into a low-loss feed structure with highly developed and inexpensive manufacturing processes. Waveguide slot radiators comprise some of the highest performance—in terms of side-lobe-level, efficiency, etc. — antenna arrays ever constructed. A wealth of information is available in the open literature regarding design procedures for linearly polarized waveguide slots. By contrast, despite their presence in some of the earliest published reports, little has been presented to date on array designs for circularly polarized (CP) waveguide slots. Moreover, that which has been presented features a classic traveling wave, efficiency-reducing beam tilt. This work proposes a unique CP waveguide slot architecture which mitigates these problems and a thorough design procedure employing widely available, modern computational tools. The proposed array topology features simultaneous dual-CP operation with grating-lobe-free, broadside radiation, high aperture efficiency, and good return loss. A traditional X-Slot CP element is employed with the inclusion of a slow wave structure passive phase shifter to ensure broadside radiation without the need for performance-limiting dielectric loading. It is anticipated this technology will be advantageous for upcoming polarimetric radar and Ka-band SatCom systems. The presented design methodology represents a philosophical shift away from traditional waveguide slot radiator design practices. Rather than providing design curves and/or analytical expressions for equivalent circuit models, simple first-order design rules – generated via parametric studies — are presented with the understanding that device optimization and design will be carried out computationally. A unit-cell, S-parameter based approach provides a sufficient reduction of complexity to permit efficient, accurate device design with attention to realistic, application-specific mechanical tolerances. A transparent, start-to-finish example of the design procedure for a linear sub-array at X-Band is presented. Both unit cell and array performance is calculated via finite element method simulations. Results are confirmed via good agreement with finite difference, time domain calculations. Array performance exhibiting grating-lobe-free, broadside-scanned, dual-CP radiation with better than 20 dB return loss and over 75% aperture efficiency is presented.

Design and implementation of a 3D computer game controller using inertial MEMS sensors

Though 3D computer graphics has seen tremendous advancement in the past two decades, most available mechanisms for computer interaction in 3D are high cost and targeted for industry and virtual reality applications. Recent advances in Micro-Electro-Mechanical-System (MEMS) devices have brought forth a variety of new low-cost, low-power, miniature sensors with high accuracy, which are well suited for hand-held devices. In this work a novel design for a 3D computer game controller using inertial sensors is proposed, and a prototype device based on this design is implemented. The design incorporates MEMS accelerometers and gyroscopes from Analog Devices to measure the three components of the acceleration and angular velocity. From these sensor readings, the position and orientation of the hand-held compartment can be calculated using numerical methods. The implemented prototype is utilizes a USB 2.0 compliant interface for power and communication with the host system. A Microchip dsPIC microcontroller is used in the design. This microcontroller integrates the analog to digital converters, the program memory flash, as well as the core processor, on a single integrated circuit. A PC running Microsoft Windows operating system is used as the host machine. Prototype firmware for the microcontroller is developed and tested to establish the communication between the design and the host, and perform the data acquisition and initial filtering of the sensor data. A PC front-end application with a graphical interface is developed to communicate with the device, and allow real-time visualization of the acquired data.

Inductive-Capacitive Resonant Circuit Sensors for Structural Health and Environmental Monitoring

Inductive-capacitive (LC) resonant circuit sensors are low-cost, wireless, durable, simple to fabricate and battery-less. Consequently, they are well suited to sensing applications in harsh environments or in situations where large numbers of sensors are needed. They are also advantageous in applications where access to the sensor is limited or impossible or when sensors are needed on a disposable basis. Due to their many advantages, LC sensors have been used for sensing a variety of parameters including humidity, temperature, chemical concentrations, pH, stress/pressure, strain, food quality and even biological growth. However, current versions of the LC sensor technology are limited to sensing only one parameter. The purpose of this work is to develop new types of LC sensor systems that are simpler to fabricate (hence lower cost) or capable of monitoring multiple parameters simultaneously. One design presented in this work, referred to as the multi-element LC sensor, is able to measure multiple parameters simultaneously using a second capacitive element. Compared to conventional LC sensors, this design can sense multiple parameters with a higher detection range than two independent sensors while maintaining the same overall sensor footprint. In addition, the two-element sensor does not suffer from interference issues normally encountered while implementing two LC sensors in close proximity. Another design, the single-spiral inductive-capacitive sensor, utilizes the parasitic capacitance of a coil or spring structure to form a single layer LC resonant circuit. Unlike conventional LC sensors, this design is truly planar, thus simplifying its fabrication process and reducing sensor cost. Due to the simplicity of this sensor layout it will be easier and more cost-effective for embedding in common building or packaging materials during manufacturing processes, thereby adding functionality to current products (such as drywall sheets) while having a minor impact on overall unit cost. These modifications to the LC sensor design significantly improve the functionality and commercial feasibility of this technology, especially for applications where a large array of sensors or multiple sensing parameters are required.

A 45nm CMOS DESIGN OF NEUROMORPHIC SYSTEM

Neuromorphic computing has become an emerging field in wide range of applications. Its challenge lies in developing a brain-inspired architecture that can emulate human brain and can work for real time applications. In this report a flexible neural architecture is presented which consists of 128 X 128 SRAM crossbar memory and 128 spiking neurons. For Neuron, digital integrate and fire model is used. All components are designed in 45nm technology node. The core can be configured for certain Neuron parameters, Axon types and synapses states and are fully digitally implemented. Learning for this architecture is done offline. To train this circuit a well-known algorithm Restricted Boltzmann Machine (RBM) is used and linear classifiers are trained at the output of RBM. Finally, circuit was tested for handwritten digit recognition application. Future prospects for this architecture are also discussed.

Optical Waveguides and Structures for Short Haul Optical Communication Channels within Printed Circuit Boards

Optical waveguides have shown promising results for use within printed circuit boards. These optical waveguides have higher bandwidth than traditional copper transmission systems and are immune to electromagnetic interference. Design parameters for these optical waveguides are needed to ensure an optimal link budget. Modeling and simulation methods are used to determine the optimal design parameters needed in designing the waveguides. As a result, optical structures necessary for incorporating optical waveguides into printed circuit boards are designed and optimized. Embedded siloxane polymer waveguides are investigated for their use in optical printed circuit boards. This material was chosen because it has low absorption, high temperature stability, and can be deposited using common processing techniques. Two sizes of waveguides are investigated, 50 $unit{mu m}$ multimode and 4 - 9 $unit{mu m}$ single mode waveguides. A beam propagation method is developed for simulating the multimode and single mode waveguide parameters. The attenuation of simulated multimode waveguides are able to match the attenuation of fabricated waveguides with a root mean square error of 0.192 dB. Using the same process as the multimode waveguides, parameters needed to ensure a low link loss are found for single mode waveguides including maximum size, minimum cladding thickness, minimum waveguide separation, and minimum bend radius. To couple light out-of-plane to a transmitter or receiver, a structure such as a vertical interconnect assembly (VIA) is required. For multimode waveguides the optimal placement of a total internal reflection mirror can be found without prior knowledge of the waveguide length. The optimal placement is found to be either 60 µm or 150 µm away from the end of the waveguide depending on which metric a designer wants to optimize the average output power, the output power variance, or the maximum possible power loss. For single mode waveguides a volume grating coupler is designed to couple light from a silicon waveguide to a polymer single mode waveguide. A focusing grating coupler is compared to a perpendicular grating coupler that is focused by a micro-molded lens. The focusing grating coupler had an optical loss of over -14 dB, while the grating coupler with a lens had an optical loss of -6.26 dB.

IMPROVEMENTS IN SUSTAINABILITY OF GRAVITY-FED WATER SYSTEMS IN THE COMARCA NGÄBE-BUGLÉ, PANAMA: SPRING CAPTURES AND CIRCUIT RIDER MODEL

Gravity-flow aqueducts are used to bring clean water from mountain springs in the Comarca Ngäbe-Buglé, Panama, to the homes of the indigenous people who reside there. Spring captures enclose a spring to direct the flow of water into the transmission line. Seepage contact springs are most common, with water appearing above either hard basalt bedrock or a dense clay layer. Spring flows vary dramatically during wet and dry seasons, and discharge points of springs can shift, sometimes enough to impact the capture structure and its ability to properly collect all of the available water. Traditionally, spring captures are concrete boxes. The spring boxes observed by the author were dilapidated or out of alignment with the spring itself, only capturing part of the discharge. An improved design approach was developed that mimics the terrain surrounding the spring source to address these issues. Over the course of a year, three different spring sites were evaluated, and spring captures were designed and constructed based on the new approach. Spring flow data from each case study demonstrate increased flow capture in the improved structures. Rural water systems, including spring captures, can be sustainably maintained by the Circuit Rider model, a technical support system in which technical assistance is provided for the operation of the water systems. During 2012-2013, the author worked as a Circuit Rider and facilitated a water system improvement project while exploring methods of community empowerment to increase the capacity for system maintenance. Based on these experiences, recommendations are provided to expand the Circuit Rider model in the Comarca Ngäbe-Buglé under the Panamanian Ministry of Health’s Water and Sanitation Project (PASAP)

Strategic Optimization Techniques For FRTU Deployment and Chip Physical Design

Combinatorial optimization is a complex engineering subject. Although formulation often depends on the nature of problems that differs from their setup, design, constraints, and implications, establishing a unifying framework is essential. This dissertation investigates the unique features of three important optimization problems that can span from small-scale design automation to large-scale power system planning: (1) Feeder remote terminal unit (FRTU) planning strategy by considering the cybersecurity of secondary distribution network in electrical distribution grid, (2) physical-level synthesis for microfluidic lab-on-a-chip, and (3) discrete gate sizing in very-large-scale integration (VLSI) circuit. First, an optimization technique by cross entropy is proposed to handle FRTU deployment in primary network considering cybersecurity of secondary distribution network. While it is constrained by monetary budget on the number of deployed FRTUs, the proposed algorithm identi?es pivotal locations of a distribution feeder to install the FRTUs in different time horizons. Then, multi-scale optimization techniques are proposed for digital micro?uidic lab-on-a-chip physical level synthesis. The proposed techniques handle the variation-aware lab-on-a-chip placement and routing co-design while satisfying all constraints, and considering contamination and defect. Last, the first fully polynomial time approximation scheme (FPTAS) is proposed for the delay driven discrete gate sizing problem, which explores the theoretical view since the existing works are heuristics with no performance guarantee. The intellectual contribution of the proposed methods establishes a novel paradigm bridging the gaps between professional communities.