Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Charge and spin transport in nanoscale junction from first principles

Recently nanoscale junctions consisting of 0-D nanostructures (single molecule) or 1-D nanostructures (semiconducting nanowire) sandwiched between two metal electrodes are successfully fabricated and characterized. What lacks in the recent developments is the understanding of the mechanism behind the observed phenomena at the level of atoms and electrons. For example, the origin of observed switching effect in a semiconducting nanowire due to the influence of an external gate bias is not yet understood at the electronic structure level. On the same context, different experimental groups have reported different signs in tunneling magneto-resistance for the same organic spin valve structure, which has baffled researchers working in this field. In this thesis, we present the answers to some of these subtle questions by investigating the charge and spin transport in different nanoscale junctions. A parameter-free, single particle Green’s function approach in conjunction with a posteriori density functional theory (DFT) involving a hybrid orbital dependent functional is used to calculate the tunneling current in the coherent transport limit. The effect of spin polarization is explicitly incorporated to investigate spin transport in a nanoscale junction. Through the electron transport studies in PbS nanowire junction, a new orbital controlled mechanism behind the switching of the current is proposed. It can explain the switching behavior, not only in PbS nanowire, but in other lead-chalcogenide nanowires as well. Beside this, the electronic structure properties of this nanowire are studied using periodic DFT. The quantum confinement effect was investigated by calculating the bandgap of PbS nanowires with different diameters. Subsequently, we explain an observed semiconducting to metallic phase transition of this nanowire by calculating the bandgap of the nanowire under uniform radial strain. The compressive radial strain on the nanowire was found to be responsible for the metallic to semiconducting phase transition. Apart from studying one dimensional nanostructure, we also present transport properties in zero dimensional single molecular junctions. We proposed a new codoping approach in a single molecular carborane junction, where a cation and an anion are simultaneously doped to find the role of a single atom in the device. The main purpose was to build a molecular junction where a single atom can dictate the flow of electrons in a circuit. Recent observations of both positive and negative sign in tunneling magnetoresistance (TMR) the using same organic spin-valve structure hasmystified researchers. From our spin dependent transport studies in a prototypical organic molecular tunneling device, we found that a 3% change in metal-molecule interfacial distance can alter the sign of TMR. Changing the interfacial distance by 3%, the number of participating eigenstates as well as their orbital characteristic changes for anti-parallel configuration of the magnetization at the two electrodes, leading to the sign reversal of the TMR. Apart from this, the magnetic proximity effect under applied bias is investigated quantitatively, which can be used to understand the observed unexpectedmagnetismin carbon basedmaterials when they are in close proximity with magnetic substrates.

STOCHASTIC CHARGE TRANSPORT IN MULTI-ISLAND SINGLE-ELECTRON TUNNELING DEVICES

The physics of the operation of singe-electron tunneling devices (SEDs) and singe-electron tunneling transistors (SETs), especially of those with multiple nanometer-sized islands, has remained poorly understood in spite of some intensive experimental and theoretical research. This computational study examines the current-voltage (IV) characteristics of multi-island single-electron devices using a newly developed multi-island transport simulator (MITS) that is based on semi-classical tunneling theory and kinetic Monte Carlo simulation. The dependence of device characteristics on physical device parameters is explored, and the physical mechanisms that lead to the Coulomb blockade (CB) and Coulomb staircase (CS) characteristics are proposed. Simulations using MITS demonstrate that the overall IV characteristics in a device with a random distribution of islands are a result of a complex interplay among those factors that affect the tunneling rates that are fixed a priori (e.g. island sizes, island separations, temperature, gate bias, etc.), and the evolving charge state of the system, which changes as the source-drain bias (VSD) is changed. With increasing VSD, a multi-island device has to overcome multiple discrete energy barriers (up-steps) before it reaches the threshold voltage (Vth). Beyond Vth, current flow is rate-limited by slow junctions, which leads to the CS structures in the IV characteristic. Each step in the CS is characterized by a unique distribution of island charges with an associated distribution of tunneling probabilities. MITS simulation studies done on one-dimensional (1D) disordered chains show that longer chains are better suited for switching applications as Vth increases with increasing chain length. They are also able to retain CS structures at higher temperatures better than shorter chains. In sufficiently disordered 2D systems, we demonstrate that there may exist a dominant conducting path (DCP) for conduction, which makes the 2D device behave as a quasi-1D device. The existence of a DCP is sensitive to the device structure, but is robust with respect to changes in temperature, gate bias, and VSD. A side gate in 1D and 2D systems can effectively control Vth. We argue that devices with smaller island sizes and narrower junctions may be better suited for practical applications, especially at room temperature.