Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Immobilizing bacteriorhodopsin on a single electron transistor

As awareness of potential human and environmental impacts from toxins has increased, so has the development of innovative sensors. Bacteriorhodopsin (bR) is a light activated proton pump contained in the purple membrane (PM) of the bacteria Halobacterium salinarum. Bacteriorhodopsin is a robust protein which can function in both wet and dry states and can withstand extreme environmental conditions. A single electron transistor(SET) is a nano-scale device that exploits the quantum mechanical properties of electrons to switch on and off. SETs have tremendous potential in practical applications due to their size, ultra low power requirements, and electrometer-like sensitivity. The main goal of this research was to create a bionanohybrid device by integrating bR with a SET device. This was achieved by a multidisciplinary approach. The SET devices were created by a combination of sputtering, photolithography, and focused ion beam machining. The bionanomaterial bacteriorhodopsin was created through oxidative fermentation and a series of transmembrane purification processes. The bR was then integrated with the SET by electrophoretic deposition, creating a bionanohybrid device. The bionanohybrid device was then characterized using a semiconductor parametric analyzer. Characterization demonstrated that the bR modulated the operational characteristics of the SET when bR was activated with light within its absorbance spectrum. To effectively integrate bacteriorhodopsin with microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS), it is critical to know the electrical properties of the material and to understand how it will affect the functionality of the device. Tests were performed on dried films of bR to determine if there is a relationship between inductance, capacitance, and resistance (LCR) measurements and orientation, light-on/off, frequency, and time. The results indicated that the LCR measurements of the bR depended on the thickness and area of the film, but not on the orientation, as with other biological materials such as muscle. However, there was a transient LCR response for both oriented and unoriented bR which depended on light intensity. From the impedance measurements an empirical model was suggested for the bionanohybrid device. The empirical model is based on the dominant electrical characteristics of the bR which were the parallel capacitance and resistance. The empirical model suggests that it is possible to integrate bR with a SET without influencing its functional characteristics.

A 45nm CMOS DESIGN OF NEUROMORPHIC SYSTEM

Neuromorphic computing has become an emerging field in wide range of applications. Its challenge lies in developing a brain-inspired architecture that can emulate human brain and can work for real time applications. In this report a flexible neural architecture is presented which consists of 128 X 128 SRAM crossbar memory and 128 spiking neurons. For Neuron, digital integrate and fire model is used. All components are designed in 45nm technology node. The core can be configured for certain Neuron parameters, Axon types and synapses states and are fully digitally implemented. Learning for this architecture is done offline. To train this circuit a well-known algorithm Restricted Boltzmann Machine (RBM) is used and linear classifiers are trained at the output of RBM. Finally, circuit was tested for handwritten digit recognition application. Future prospects for this architecture are also discussed.

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling.