Stability analysis of a mono inverter dual sensorless motors system

When a single brush-less dc motor is fed by an inverter with a sensor-less algorithm embedded in the switching controller, the system exhibits a linear and stable output in terms of the speed and torque. However, with two motors modulated by the same inverter, the system is unstable and rendered useless for a steady application, unless provided with some resistive damping on the supply lines. The project discusses and analysis the stability of such a system through simulations and hardware demonstrations and also will discuss a method to derive the values of these damping.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

A 45nm CMOS DESIGN OF NEUROMORPHIC SYSTEM

Neuromorphic computing has become an emerging field in wide range of applications. Its challenge lies in developing a brain-inspired architecture that can emulate human brain and can work for real time applications. In this report a flexible neural architecture is presented which consists of 128 X 128 SRAM crossbar memory and 128 spiking neurons. For Neuron, digital integrate and fire model is used. All components are designed in 45nm technology node. The core can be configured for certain Neuron parameters, Axon types and synapses states and are fully digitally implemented. Learning for this architecture is done offline. To train this circuit a well-known algorithm Restricted Boltzmann Machine (RBM) is used and linear classifiers are trained at the output of RBM. Finally, circuit was tested for handwritten digit recognition application. Future prospects for this architecture are also discussed.

SVPWM SWITCHING PATTERN FOR Z-SOURCE INVERTER, SIMULATION AND APPLICATION

The voltage source inverter (VSI) and current voltage source inverter (CSI) are widely used in industrial application. But the traditional VSIs and CSIs have one common problem: can’t boost or buck the voltage come from battery, which make them impossible to be used alone in Hybrid Electric Vehicle (HEV/EV) motor drive application, other issue is the traditional inverter need to add the dead-band time into the control sequence, but it will cause the output waveform distortion. This report presents an impedance source (Z-source network) topology to overcome these problems, it can use one stage instead of two stages (VSI or CSI + boost converter) to buck/boost the voltage come from battery in inverter system. Therefore, the Z-source topology hardware design can reduce switching element, entire system size and weight, minimize the system cost and increase the system efficiency. Also, a modified space vector pulse-width modulation (SVPWM) control method has been selected with the Z-source network together to achieve the best efficiency and lower total harmonic distortion (THD) at different modulation indexes. Finally, the Z-source inverter controlling will modulate under two control sequences: sinusoidal pulse width modulation (SPWM) and SVPWM, and their output voltage, ripple and THD will be compared.