Performance evaluation and characterization of symmetric capacitors with carbon black, and asymmetric capacitors using a carbon foam supported nickel electrode

This thesis evaluates a novel asymmetric capacitor incorporating a carbon foam supported nickel hydroxide positive electrode and a carbon black negative electrode. A series of symmetric capacitors were prepared to characterize the carbon black (CB) negative electrode. The influence of the binder, PTFE, content on the cell properties was evaluated. X-ray diffraction characterization of the nickel electrode during cycling is also presented. The 3 wt% and 5 wt% PTFE/CB symmetric cells were examined using cyclic voltammetry (CV) and constant current charge/discharge measurements. As compared with symmetric cells containing more PTFE, the 3 wt% cell has the highest average specific capacitance, energy density and power density over 300 cycles, 121.8 F/g, 6.44 Wh/kg, and 604.1 W/kg, respectively. Over the 3 to 10 wt% PTFE/CB range, the 3 wt% sample exhibited the lowest effective resistance and the highest BET surface area. Three asymmetric cells (3 wt% PTFE/CB negative electrode and a nickel positive) were fabricated; cycle life was examined at 3 current densities. The highest average energy and power densities over 1000 cycles were 20 Wh/kg (21 mA/cm2) and 715 W/kg (31 mA/cm2), respectively. The longest cycle life was 11,505 cycles (at 8 mA/cm2), with an average efficiency of 79% and an average energy density of 14 Wh/kg. The XRD results demonstrate that the cathodically deposited nickel electrode is a typical α-Ni(OH)2 with the R3m structure (ABBCCA stacking); the charged electrodes are 3γ-NiOOH with the same stacking as the α-type; the discharged electrodes (including as-formed electrode) are aged to β’-Ni(OH)2 (a disordered β) with the P3m structure (ABAB stacking). A 3γ remnant was observed.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

A 45nm CMOS DESIGN OF NEUROMORPHIC SYSTEM

Neuromorphic computing has become an emerging field in wide range of applications. Its challenge lies in developing a brain-inspired architecture that can emulate human brain and can work for real time applications. In this report a flexible neural architecture is presented which consists of 128 X 128 SRAM crossbar memory and 128 spiking neurons. For Neuron, digital integrate and fire model is used. All components are designed in 45nm technology node. The core can be configured for certain Neuron parameters, Axon types and synapses states and are fully digitally implemented. Learning for this architecture is done offline. To train this circuit a well-known algorithm Restricted Boltzmann Machine (RBM) is used and linear classifiers are trained at the output of RBM. Finally, circuit was tested for handwritten digit recognition application. Future prospects for this architecture are also discussed.