DESIGN OF A LIQUID FUEL INJECTOR FOR ALTERNATIVE FUEL STUDIES IN AN ATMOSPHERIC MODEL GAS TURBINE COMBUSTOR

A new liquid-fuel injector was designed for use in the atmospheric-pressure, model gas turbine combustor in Bucknell University’s Combustion Research Laboratory during alternative fuel testing. The current liquid-fuel injector requires a higher-than-desired pressure drop and volumetric flow rate to provide proper atomization of liquid fuels. An air-blast atomizer type of fuel injector was chosen and an experiment utilizing water as the working fluid was performed on a variable-geometry prototype. Visualization of the spray pattern was achieved through photography and the pressure drop was measured as a function of the required operating parameters. Experimental correlations were used to estimate droplet sizes over flow conditions similar to that which would be experienced in the actual combustor. The results of this experiment were used to select the desired geometric parameters for the proposed final injector design and a CAD model was generated. Eventually, the new injector will be fabricated and tested to provide final validation of the design prior to use in the combustion test apparatus.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.