Solar thermal decoupled water electrolysis process I: Proof of concept

A new concept for a solar thermal electrolytic process was developed for the production of H-2 from water. A metal oxide is reduced to a lower oxidation state in air with concentrated solar energy. The reduced oxide is then used either as an anode or solute for the electrolytic production of H-2 in either an aqueous acid or base solution. The presence of the reduced metal oxide as part of the electrolytic cell decreases the potential required for water electrolysis below the ideal 1.23 V required when H-2 and O-2 evolve at 1 bar and 298 K. During electrolysis, H-2 evolves at the cathode at 1 bar while the reduced metal oxide is returned to its original oxidation state, thus completing the H-2 production cycle. Ideal sunlight-to-hydrogen thermal efficiencies were established for three oxide systems: Fe2O3-Fe3O4, Co3O4-CoO, and Mn2O3-Mn3O4. The ideal efficiencies that include radiation heat loss are as high or higher than corresponding ideal values reported in the solar thermal chemistry literature. An exploratory experimental study for the iron oxide system confirmed that the electrolytic and thermal reduction steps occur in a laboratory scale environment.

3CAM - A NOVEL TERNARY CONTENT ADDRESSABLE MEMORY USING THREE-VALUED LOGIC

Content Addressable Memory (CAM) is a special type of Complementary Metal-Oxide-Semiconductor (CMOS) storage element that allows for a parallel search operation on a memory stack in addition to the read and write operations yielded by a conventional SRAM storage array. In practice, it is often desirable to be able to store a “don’t care” state for faster searching operation. However, commercially available CAM chips are forced to accomplish this functionality by having to include two binary memory storage elements per CAM cell,which is a waste of precious area and power resources. This research presents a novel CAM circuit that achieves the “don’t care” functionality with a single ternary memory storage element. Using the recent development of multiple-voltage-threshold (MVT) CMOS transistors, the functionality of the proposed circuit is validated and characteristics for performance, power consumption, noise immunity, and silicon area are presented. This workpresents the following contributions to the field of CAM and ternary-valued logic:• We present a novel Simple Ternary Inverter (STI) transistor geometry scheme for achieving ternary-valued functionality in existing SOI-CMOS 0.18µm processes.• We present a novel Ternary Content Addressable Memory based on Three-Valued Logic (3CAM) as a single-storage-element CAM cell with “don’t care” functionality.• We explore the application of macro partitioning schemes to our proposed 3CAM array to observe the benefits and tradeoffs of architecture design in the context of power, delay, and area.