Hibernacula Microclimate and White-nose Syndrome Susceptibility in the Little Brown Myotis (Myotis lucifugus)

The objective of this project was to determine the relationship between hibernacula microclimate and White-nose Syndrome (WNS), an emerging infectious disease in bats. Microclimate was examined on a species scale and at the level of the individual bat to determine if there was a difference in microclimate preference between healthy and WNS-affected little brown myotis (Myotis lucifugus) and to determine the role of microclimate in disease progression. There is anecdotal evidence that colder, drier hibernacula are less affected by WNS. This was tested by placing rugged temperature and humidity dataloggers in field sites throughout the eastern USA, experimentally determining the response to microclimate differences in captive bats, and testing microclimate roosting preference. This study found that microclimate significantly differed from the entrance of a hibernaculum versus where bats traditionally roost. It also found hibernaculum temperature and sex had significant impacts on survival in WNS-affected bats. Male bats with WNS had increased survivability over WNS-affected female bats and WNS bats housed below the ideal growth range of the fungus that causes WNS, Geomyces destructans, had increased survival over those housed at warmer temperatures. The results from this study are immediately applicable to (1) predict which hibernacula are more likely to be infected next winter, (2) further our understanding of WNS, and (3) determine if direct mitigation strategies, such as altering the microclimate of mines, will be effective ways to combat the spread of the fungus.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.