Maternal and Postweaning High-Fat Diets Disturb Hippocampal Gene Expression, Learning, and Memory Function

We tested the hypothesis that excess saturated fat consumption during pregnancy, lactation, and/or postweaning alters the expression of genes mediating hippocampal synaptic efficacy and impairs spatial learning and memory in adulthood. Dams were fed control chow or a diet high in saturated fat before mating, during pregnancy, and into lactation. Offspring were weaned to either standard chow or a diet high in saturated fat. The Morris Water Maze was used to evaluate spatial learning and memory. Open field testing was used to evaluate motor activity. Hippocampal gene expression in adult males was measured using RT-PCR and ELISA. Offspring from high fat-fed dams took longer, swam farther, and faster to try and find the hidden platform during the 5-day learning period. Control offspring consuming standard chow spent the most time in memory quadrant during the probe test. Offspring from high fat-fed dams consuming excess saturated fat spent the least. The levels of mRNA and protein for brain-derived neurotrophic factor and activity-regulated cytoskeletal-associated protein were significantly decreased by maternal diet effects. Nerve growth factor mRNA and protein levels were significantly reduced in response to both maternal and postweaning high-fat diets. Expression levels for the N-methyl-D-aspartate receptor (NMDA) receptor subunit NR2B as well as synaptophysin were significantly decreased in response to both maternal and postweaning diets. Synaptotagmin was significantly increased in offspring from high fat-fed dams. These data support the hypothesis that exposure to excess saturated fat during hippocampal development is associated with complex patterns of gene expression and deficits in learning and memory.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.