Integrated Geophysical Investigation of the St. James Fault Complex: A Case Study

We noninvasively detected the characteristics and location of a regional fault in an area of poor bedrock exposure complicated by karst weathering features in the subsurface. Because this regional fault is associated with sinkhole formation, its location is important for hazard avoidance. The bedrock lithologies on either side of the fault trace are similar; hence, we chose an approach that capitalized on the complementary strengths of very low frequency (VLF) electromagnetic, resistivity, and gravity methods. VLF proved most useful as a first-order reconnaissance tool, allowing us to define a narrow target area for further geophysical exploration. Fault-related epikarst was delineated using resistivity. Ultimately, a high-resolution gravity survey and subsequent inverse modeling using the results of the resistivity survey helped to further constrain the location and approximate orientation of the fault. The combined results indicated that the location of the fault trace needed to be adjusted 53 m south of the current published location and was consistent with a north-dipping thrust fault. Additionally, a gravity low south of the fault trace agreed with the location of conductive material from the resistivity and VLF surveys. We interpreted these anomalies to represent enhanced epikarst in the fault footwall. We clearly found that a staged approach involving a progression of methods beginning with a reconnaissance VLF survey, followed by high-resolution gravity and electrical resistivity surveys, can be used to characterize a fault and fault-related karst in an area of poor bedrock surface exposure.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.