2 resultados para TIRE CHIPS

em Bucknell University Digital Commons - Pensilvania - USA


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Recent developments in vehicle steering systems offer new opportunities to measure the steering torque and reliably estimate the vehicle sideslip and the tire-road friction coefficient. This paper presents an approach to vehicle stabilization that leverages these estimates to define state boundaries that exclude unstable vehicle dynamics and utilizes a model predictive envelope controller to bound the vehicle motion within this stable region of the state space. This approach provides a large operating region accessible by the driver and smooth interventions at the stability boundaries. Experimental results obtained with a steer-by-wire vehicle and a proof of envelope invariance demonstrate the efficacy of the envelope controller in controlling the vehicle at the limits of handling.

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Content Addressable Memory (CAM) is a special type of Complementary Metal-Oxide-Semiconductor (CMOS) storage element that allows for a parallel search operation on a memory stack in addition to the read and write operations yielded by a conventional SRAM storage array. In practice, it is often desirable to be able to store a “don’t care” state for faster searching operation. However, commercially available CAM chips are forced to accomplish this functionality by having to include two binary memory storage elements per CAM cell,which is a waste of precious area and power resources. This research presents a novel CAM circuit that achieves the “don’t care” functionality with a single ternary memory storage element. Using the recent development of multiple-voltage-threshold (MVT) CMOS transistors, the functionality of the proposed circuit is validated and characteristics for performance, power consumption, noise immunity, and silicon area are presented. This workpresents the following contributions to the field of CAM and ternary-valued logic:• We present a novel Simple Ternary Inverter (STI) transistor geometry scheme for achieving ternary-valued functionality in existing SOI-CMOS 0.18µm processes.• We present a novel Ternary Content Addressable Memory based on Three-Valued Logic (3CAM) as a single-storage-element CAM cell with “don’t care” functionality.• We explore the application of macro partitioning schemes to our proposed 3CAM array to observe the benefits and tradeoffs of architecture design in the context of power, delay, and area.