Play!

Play is a scholarly topic with a long and convoluted history. This faculty colloquium will make a few obligatory nods to the literature, but then focus instead on how play might be related to the Bucknell educational mission. The talk will be structured more in the spirit of a “This I Believe” essay. It is meant to challenge the Bucknell community to consider play as an important component of a healthy environment. Some questions we will visit: Why as we mature do we view play as the opposite of work? How can play be used to practice skills and explore our world-view? What is the connection between play and creative habits? How can we pair play with reflection to stimulate deep learning? How might we alter our risk/reward structures to encourage productive play?

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.