Human Preferences for Symmetry: Subjective Experience, Cognitive Conflict and Cortical Brain Activity

This study examines the links between human perceptions, cognitive biases and neural processing of symmetrical stimuli. While preferences for symmetry have largely been examined in the context of disorders such as obsessive-compulsive disorder and autism spectrum disorders, we examine various these phenomena in non-clinical subjects and suggest that such preferences are distributed throughout the typical population as part of our cognitive and neural architecture. In Experiment 1, 82 young adults reported on the frequency of their obsessive-compulsive spectrum behaviors. Subjects also performed an emotional Stroop or variant of an Implicit Association Task (the OC-CIT) developed to assess cognitive biases for symmetry. Data not only reveal that subjects evidence a cognitive conflict when asked to match images of positive affect with asymmetrical stimuli, and disgust with symmetry, but also that their slowed reaction times when asked to do so were predicted by reports of OC behavior, particularly checking behavior. In Experiment 2, 26 participants were administered an oddball Event-Related Potential task specifically designed to assess sensitivity to symmetry as well as the OC-CIT. These data revealed that reaction times on the OC-CIT were strongly predicted by frontal electrode sites indicating faster processing of an asymmetrical stimulus (unparallel lines) relative to a symmetrical stimulus (parallel lines). The results point to an overall cognitive bias linking disgust with asymmetry and suggest that such cognitive biases are reflected in neural responses to symmetrical/asymmetrical stimuli.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.