Active processes, morphology, and dynamics of icy debris fans: Landform evolution along rapidly degrading escarpments in alpine regions undergoing recent deglaciation

In the past few decades the impacts of climate warming have been significant in alpine glaciated regions. Many valley glaciers formerly linked as distributary glaciers to high-level icecaps have decoupled at their icefalls, exposing major escarpments and generating a suite of dynamic landforrns dominated by mass wasting. Ice-dominated landforms, here termed icy debris fans, develop rapidly by ice avalanching, rockfall, and icy debris flow. Field-based reconnaissance studies at two alpine settings, the Wrangell Mountains of Alaska and the Southern Alps of New Zealand, provide a preliminary morphogenetic model of spatial and temporal evolution of icy debris fans in a range of alpine settings. The influence of these processes on landform evolution is largely unrecognized in the literature dealing with post-glacial landform adjustment known as the paraglacial. A better understanding of these dynamic processes will be increasingly important because of the extreme geohazards characterizing these areas. Our field studies show that after glacier decoupling, icy debris fans begin to form along the base of bedrock escarpments at the mouths of catchments and prograde over valley glaciers. The presence of a distinct catchment, apex, and fan morphology distinguishes these landforms from other landforms common in periglacial hillslope settings receiving abundant clastic debris and ice. Ice avalanching is the most abundant process involved in icy debris fan formation. Fans developed below weakly incised catchments are dominated by ice avalanching and are composed primarily of ice with minor lithic detritus. Typically, avalanches fall into the fan catchments where sediments transform into grainflows that flow onto the fans. Once on the fans, avalanche deposits ablate rapidly, flattening and concentrating lithic fragments at the surface. Icy debris fans may become thick enough to become glaciers with splay crevasse systems. Fans developed below larger, more complex catchments are composed of higher proportions of lithic detritus resulting from temporary storage of ice and lithic detritus deposits within the catchment. Episodic outbursts of meltwater from the icecap may mix with the stored sediments and mobilize icy debris flows (mixture of ice and lithic clasts) onto the fans. Our observations indicate that the entire evolutionary cycle of icy debris fans probably occurs during an early paraglacial interval (i.e., decades to 100 years). Observations comparing avalanche frequency, volume, and fan morphologic evolution at the Alaska site between 2006 and 2010 illustrate complex response between icy debris fans even within the same cirque - where one fan may be growing while others are downwasting because of differences in ice supply controlled by their respective catchments and icecap contributions. As ice supply from the icecap diminishes through time, icy debris fans rapidly downwaste and eventually evolve into talus cones that receive occasional but ephemeral ice avalanches.

Integrated Geophysical Investigation of the St. James Fault Complex: A Case Study

We noninvasively detected the characteristics and location of a regional fault in an area of poor bedrock exposure complicated by karst weathering features in the subsurface. Because this regional fault is associated with sinkhole formation, its location is important for hazard avoidance. The bedrock lithologies on either side of the fault trace are similar; hence, we chose an approach that capitalized on the complementary strengths of very low frequency (VLF) electromagnetic, resistivity, and gravity methods. VLF proved most useful as a first-order reconnaissance tool, allowing us to define a narrow target area for further geophysical exploration. Fault-related epikarst was delineated using resistivity. Ultimately, a high-resolution gravity survey and subsequent inverse modeling using the results of the resistivity survey helped to further constrain the location and approximate orientation of the fault. The combined results indicated that the location of the fault trace needed to be adjusted 53 m south of the current published location and was consistent with a north-dipping thrust fault. Additionally, a gravity low south of the fault trace agreed with the location of conductive material from the resistivity and VLF surveys. We interpreted these anomalies to represent enhanced epikarst in the fault footwall. We clearly found that a staged approach involving a progression of methods beginning with a reconnaissance VLF survey, followed by high-resolution gravity and electrical resistivity surveys, can be used to characterize a fault and fault-related karst in an area of poor bedrock surface exposure.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.