Entrainment and Unit Velocity: Surprises in an Accelerated Exclusion Process

We introduce a class of distance-dependent interactions in an accelerated exclusion process inspired by the observation of transcribing RNA polymerase speeding up when “pushed” by a trailing one. On a ring, the accelerated exclusion process steady state displays a discontinuous transition, from being homogeneous (with augmented currents) to phase segregated. In the latter state, the holes appear loosely bound and move together, much like a train. Surprisingly, the current-density relation is simply J=1-ρ, signifying that the “hole train” travels with unit velocity.

Entrainment and Unit Velocity: Surprises in an Accelerated Exclusion Process

We introduce a class of distance-dependent interactions in an accelerated exclusion process inspired by the observation of transcribing RNA polymerase speeding up when “pushed” by a trailing one. On a ring, the accelerated exclusion process steady state displays a discontinuous transition, from being homogeneous (with augmented currents) to phase segregated. In the latter state, the holes appear loosely bound and move together, much like a train. Surprisingly, the current-density relation is simply J=1-ρ, signifying that the “hole train” travels with unit velocity.

Mass Transport Perspective on an Accelerated Exclusion Process: Analysis of Augmented Current and Unit-Velocity Phases

In an accelerated exclusion process (AEP), each particle can "hop" to its adjacent site if empty as well as "kick" the frontmost particle when joining a cluster of size ℓ⩽ℓ_{max}. With various choices of the interaction range, ℓ_{max}, we find that the steady state of AEP can be found in a homogeneous phase with augmented currents (AC) or a segregated phase with holes moving at unit velocity (UV). Here we present a detailed study on the emergence of the novel phases, from two perspectives: the AEP and a mass transport process (MTP). In the latter picture, the system in the UV phase is composed of a condensate in coexistence with a fluid, while the transition from AC to UV can be regarded as condensation. Using Monte Carlo simulations, exact results for special cases, and analytic methods in a mean field approach (within the MTP), we focus on steady state currents and cluster sizes. Excellent agreement between data and theory is found, providing an insightful picture for understanding this model system.

FPGA BASED DESIGN FOR ACCELERATED FAULT-TESTING OF INTEGRATED CIRCUITS

In the past few decades, integrated circuits have become a major part of everyday life. Every circuit that is created needs to be tested for faults so faulty circuits are not sent to end-users. The creation of these tests is time consuming, costly and difficult to perform on larger circuits. This research presents a novel method for fault detection and test pattern reduction in integrated circuitry under test. By leveraging the FPGA's reconfigurability and parallel processing capabilities, a speed up in fault detection can be achieved over previous computer simulation techniques. This work presents the following contributions to the field of Stuck-At-Fault detection: We present a new method for inserting faults into a circuit net list. Given any circuit netlist, our tool can insert multiplexers into a circuit at correct internal nodes to aid in fault emulation on reconfigurable hardware. We present a parallel method of fault emulation. The benefit of the FPGA is not only its ability to implement any circuit, but its ability to process data in parallel. This research utilizes this to create a more efficient emulation method that implements numerous copies of the same circuit in the FPGA. A new method to organize the most efficient faults. Most methods for determinin the minimum number of inputs to cover the most faults require sophisticated softwareprograms that use heuristics. By utilizing hardware, this research is able to process data faster and use a simpler method for an efficient way of minimizing inputs.