Design of a wearable platform for PPG analysis with multicore low-power processor

Photoplethysmography (PPG) sensors allow for noninvasive and comfortable heart-rate (HR) monitoring, suitable for compact wearable devices. However, PPG signals collected from such devices often suffer from corruption caused by motion artifacts. This is typically addressed by combining the PPG signal with acceleration measurements from an inertial sensor. Recently, different energy-efficient deep learning approaches for heart rate estimation have been proposed. To test these new solutions, in this work, we developed a highly wearable platform (42mm x 48 mm x 1.2mm) for PPG signal acquisition and processing, based on GAP9, a parallel ultra low power system-on-chip featuring nine cores RISC-V compute cluster with neural network accelerator and 1 core RISC-V controller. The hardware platform also integrates a commercial complete Optical Biosensing Module and an ARM-Cortex M4 microcontroller unit (MCU) with Bluetooth low-energy connectivity. To demonstrate the capabilities of the system, a deep learning-based approach for PPG-based HR estimation has been deployed. Thanks to the reduced power consumption of the digital computational platform, the total power budget is just 2.67 mW providing up to 5 days of operation (105 mAh battery).

Le macchine multifase nelle applicazioni Sensorless:indagine teorico-sperimentale di un azionamento basato su DSP per macchine asincrone eptafase

Fino ad un recente passato, le macchine elettriche di tipo trifase costituivano l’unica soluzione in ambito industriale per la realizzazione di azionamenti di grande potenza. Da quando i motori sono gestiti da convertitori elettronici di potenza si è ottenuto un notevole passo in avanti verso l’innovazione tecnologica. Infatti, negli ultimi decenni, le tecnologie sempre più all’avanguardia e l’aumento dell’utilizzo dell’elettronica, sia in campo civile quanto in quello industriale, hanno contribuito a una riduzione dei costi dei relativi componenti; questa situazione ha permesso di utilizzare tecnologie elaborate che in passato avevano costi elevati e quindi risultavano di scarso interesse commerciale. Nel campo delle macchine elettriche tutto questo ha permesso non solo la realizzazione di azionamenti alimentati e controllati tramite inverter, in grado di garantire prestazioni nettamente migliori di quelle ottenute con i precedenti sistemi di controllo, ma anche l’avvento di una nuova tipologia di macchine con un numero di fasi diverso da quello tradizionale trifase, usualmente impiegato nella generazione e distribuzione dell’energia elettrica. Questo fatto ha destato crescente interesse per lo studio di macchine elettriche multifase. Il campo di studio delle macchine multifase è un settore relativamente nuovo ed in grande fermento, ma è già possibile affermare che le suddette macchine sono in grado di fornire prestazioni migliori di quelle trifase. Un motore con un numero di fasi maggiore di tre presenta numerosi vantaggi: 1. la possibilità di poter dividere la potenza su più fasi, riducendo la taglia in corrente degli interruttori statici dell’inverter; 2. la maggiore affidabilità in caso di guasto di una fase; 3. la possibilità di sfruttare le armoniche di campo magnetico al traferro per ottenere migliori prestazioni in termini di coppia elettromagnetica sviluppata (riduzione dell’ampiezza e incremento della frequenza della pulsazione di coppia); 4. l’opportunità di creare azionamenti elettrici multi-motore, collegando più macchine in serie e comandandole con un unico convertitore di potenza; 5. Maggiori e più efficaci possibilità di utilizzo nelle applicazioni Sensorless. Il presente lavoro di tesi, ha come oggetto lo studio e l’implementazione di una innovativa tecnica di controllo di tipo “sensorless”, da applicare in azionamenti ad orientamento di campo per macchine asincrone eptafase. Nel primo capitolo vengono illustrate le caratteristiche e le equazioni rappresentanti il modello della macchina asincrona eptafase. Nel secondo capitolo si mostrano il banco di prova e le caratteristiche dei vari componenti. Nel terzo capitolo sono rappresentate le tecniche di modulazione applicabili per macchine multifase. Nel quarto capitolo vengono illustrati il modello del sistema implementato in ambiente Simulink ed i risultati delle simulazioni eseguite. Nel quinto capitolo viene presentato il Code Composer Studio, il programma necessario al funzionamento del DSP. Nel sesto capitolo, sono presentati e commentati i risultati delle prove sperimentali.

Design and implementation of a fft pruning engine for DSA-enabled cognitive radios.

This research work presents the design and implementation of a FFT pruning block, which is an extension to the FFT core for OFDM demodulation, enabling run-time 8 pruning of the FFT algorithm, without any restrictions on the distribution pattern of the active/inactive sub-carriers. The design and implementation of FFT processor core is not the part of this work. The whole design was prototyped on an ALTERA STRATIX V FPGA to evaluate the performance of the pruning engine. Synthesis and simulation results showed that the logic overhead introduced by the pruning block is limited to a 10% of the total resources utilization. Moreover, in presence of a medium-high scattering of the sub-carriers, power and energy consumption of the FFT core were reduced by a 30% factor.

Gpu-based many-core architecture emulation: A double level approach

The efficient emulation of a many-core architecture is a challenging task, each core could be emulated through a dedicated thread and such threads would be interleaved on an either single-core or a multi-core processor. The high number of context switches will results in an unacceptable performance. To support this kind of application, the GPU computational power is exploited in order to schedule the emulation threads on the GPU cores. This presents a non trivial divergence issue, since GPU computational power is offered through SIMD processing elements, that are forced to synchronously execute the same instruction on different memory portions. Thus, a new emulation technique is introduced in order to overcome this limitation: instead of providing a routine for each ISA opcode, the emulator mimics the behavior of the Micro Architecture level, here instructions are date that a unique routine takes as input. Our new technique has been implemented and compared with the classic emulation approach, in order to investigate the chance of a hybrid solution.

Ottimizzazione di protocolli di trasmissione dati tramite interfaccia usb implementati su fpga

La maggior parte dei moderni dispositivi e macchinari, sia ad uso civile che industriale, utilizzano sistemi elettronici che ne supervisionano e ne controllano il funzionamento. All’ interno di questi apparati è quasi certamente impiegato un sistema di controllo digitale che svolge, anche grazie alle potenzialità oggi raggiunte, compiti che fino a non troppi anni or sono erano dominio dell’ elettronica analogica, si pensi ad esempio ai DSP (Digital Signal Processor) oggi impiegati nei sistemi di telecomunicazione. Nonostante l'elevata potenza di calcolo raggiunta dagli odierni microprocessori/microcontrollori/DSP dedicati alle applicazioni embedded, quando è necessario eseguire elaborazioni complesse, time-critical, dovendo razionalizzare e ottimizzare le risorse a disposizione, come ad esempio spazio consumo e costi, la scelta ricade inevitabilmente sui dispositivi FPGA. I dispositivi FPGA, acronimo di Field Programmable Gate Array, sono circuiti integrati a larga scala d’integrazione (VLSI, Very Large Scale of Integration) che possono essere configurati via software dopo la produzione. Si differenziano dai microprocessori poiché essi non eseguono un software, scritto ad esempio in linguaggio assembly oppure in linguaggio C. Sono invece dotati di risorse hardware generiche e configurabili (denominate Configurable Logic Block oppure Logic Array Block, a seconda del produttore del dispositivo) che per mezzo di un opportuno linguaggio, detto di descrizione hardware (HDL, Hardware Description Language) vengono interconnesse in modo da costituire circuiti logici digitali. In questo modo, è possibile far assumere a questi dispositivi funzionalità logiche qualsiasi, non previste in origine dal progettista del circuito integrato ma realizzabili grazie alle strutture programmabili in esso presenti.

Applying the reactive programming paradigm: Toward a more declarative application development approach

After almost 10 years from “The Free Lunch Is Over” article, where the need to parallelize programs started to be a real and mainstream issue, a lot of stuffs did happened: • Processor manufacturers are reaching the physical limits with most of their approaches to boosting CPU performance, and are instead turning to hyperthreading and multicore architectures; • Applications are increasingly need to support concurrency; • Programming languages and systems are increasingly forced to deal well with concurrency. This thesis is an attempt to propose an overview of a paradigm that aims to properly abstract the problem of propagating data changes: Reactive Programming (RP). This paradigm proposes an asynchronous non-blocking approach to concurrency and computations, abstracting from the low-level concurrency mechanisms.

Hardware-in-the-loop implementation of single- and dual-phase shift control for dual active bridge converters in EV applications

Isolated DC-DC converters play a significant role in fast charging and maintaining the variable output voltage for EV applications. This study aims to investigate the different Isolated DC-DC converters for onboard and offboard chargers, then, once the topology is selected, study the control techniques and, finally, achieve a real-time converter model to accomplish Hardware-In-The-Loop (HIL) results. Among the different isolated DC-DC topologies, the Dual Active Bridge (DAB) converter has the advantage of allowing bidirectional power flow, which enables operating in both Grid to Vehicle (G2V) and Vehicle to Grid (V2G) modalities. Recently, DAB has been used in the offboard chargers for high voltage applications due to SiC and GaN MOSFETs; this new technology also allows the utilization of higher switching frequencies. By empowering soft switching techniques to reduce switching losses, higher switching frequency operation is possible in DAB. There are four phase shift control techniques for the DAB converter. They are Single Phase shift, Extended Phase shift, Dual Phase shift, Triple Phase shift controls. This thesis considers two control strategies; Single-Phase, and Dual-Phase shifts, to understand the circulating currents, power losses, and output capacitor size reduction in the DAB. Hardware-In-The-Loop (HIL) experiments are carried out on both controls with high switching frequencies using the PLECS software tool and the RT box supporting the PLECS. Root Mean Square Error is also calculated for steady-state values of output voltage with different sampling frequencies in both the controls to identify the achievable sampling frequency in real-time. DSP implementation is also executed to emulate the optimized DAB converter design, and final real-time simulation results are discussed for both the Single-Phase and Dual-Phase shift controls.

Embedding Video Object Detection Capabilities on Low-Power Nano-Drones

Our objective for this thesis work was the deployment of a Neural Network based approach for video object detection on board a nano-drone. Furthermore, we have studied some possible extensions to exploit the temporal nature of videos to improve the detection capabilities of our algorithm. For our project, we have utilized the Mobilenetv2/v3SSDLite due to their limited computational and memory requirements. We have trained our networks on the IMAGENET VID 2015 dataset and to deploy it onto the nano-drone we have used the NNtool and Autotiler tools by GreenWaves. To exploit the temporal nature of video data we have tried different approaches: the introduction of an LSTM based convolutional layer in our architecture, the introduction of a Kalman filter based tracker as a postprocessing step to augment the results of our base architecture. We have obtain a total improvement in our performances of about 2.5 mAP with the Kalman filter based method(BYTE). Our detector run on a microcontroller class processor on board the nano-drone at 1.63 fps.

Analysis, Design, and Hardware-in-the-Loop Validation of Multi-Active Bridge Converters

This master's thesis investigates different aspects of Dual-Active-Bridge (DAB) Converter and extends aspects further to Multi-Active-Bridges (MAB). The thesis starts with an overview of the applications of the DAB and MAB and their importance. The analytical part of the thesis includes the derivation of the peak and RMS currents, which is required for finding the losses present in the system. The power converters, considered in this thesis are DAB, Triple-Active Bridge (TAB) and Quad-Active Bridge (QAB). All the theoretical calculations are compared with the simulation results from PLECS software for identifying the correctness of the reviewed and developed theory. The Hardware-in-the-Loop (HIL) simulation is conducted for checking the control operation in real-time with the help of the RT box from the Plexim. Additionally, as in real systems digital signal processor (DSP), system-on-chip or field programmable gate array is employed for the control of the power electronic systems, and the execution of the control in the real-time simulation (RTS) conducted is performed by DSP.