3 resultados para SYNCHRONOUS CDMA

em AMS Tesi di Laurea - Alm@DL - Università di Bologna


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The increasing interest in the decarbonization process led to a rapidly growing trend of electrification strategies in the automotive industry. In particular, OEMs are pushing towards the development and production of efficient electric vehicles. Moreover, research on electric motors and their control are exploding in popularity. The increase of computational power in embedded control hardware is allowing the development of new control algorithm, such as sensorless control strategy. Such control strategy allows the reduction of the number of sensors, which implies reduced costs and increased system reliability. The thesis objective is to realize a sensorless control for high-performance automotive motors. Several algorithms for rotor angle observers are implemented in the MATLAB and Simulink environment, with emphasis on the Kalman observer. One of the Kalman algorithms already available in the literature has been selected, implemented and benchmarked, with emphasis on its comparison with the Sliding Mode observer. Different models characterized by increasing levels of complexity are simulated. A simplified synchronous motor with ”constant parameters”, controlled by an ideal inverter is first analyzed; followed by a complete model defined by real motor maps, and controlled by a switching inverter. Finally, it was possible to test the developed algorithm on a real electric motor mounted on a test bench. A wide range of different electric motors have been simulated, which led to an exhaustive review of the sensorless control algorithm. The final results underline the capability of the Kalman observer to effectively control the motor on a real test bench.

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The present work describes the different stages of design, implementation, and validation procedures for an interleaved DC-DC boost converter intended for the 2022 Futura, a fuel cell-powered racing catamaran developed by the UniBoAT team. The main goal of the entire design has been the significant reduction of the weight of the converter by removing heat sinks and reducing component size while increasing its efficiency by adopting high-end power switches and the interleaved architecture operated with a synchronous control strategy. The obtained converter has been integrated into the structure containing the fuel cell stack obtaining a fully integrated system. The realized device has been based on an interleaved architecture with six phases controlled digitally through the average current mode control. The design has been validated through simulations carried out using the software LT-Spice, whereas experimental validations have been performed by means of laboratory bench tests and on-field tests. Detailed thermal and efficiency analyses are provided with the bench tests under the two synchronous and non-synchronous operating modes and with the adoption of the phase shedding technique. The prototype implementation and its performance in real operating conditions are also discussed. Eventually, it is underlined as the designed converter can be used in other applications requiring a voltage-controlled boost converter.

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Questa dissertazione esamina le sfide e i limiti che gli algoritmi di analisi di grafi incontrano in architetture distribuite costituite da personal computer. In particolare, analizza il comportamento dell'algoritmo del PageRank così come implementato in una popolare libreria C++ di analisi di grafi distribuiti, la Parallel Boost Graph Library (Parallel BGL). I risultati qui presentati mostrano che il modello di programmazione parallela Bulk Synchronous Parallel è inadatto all'implementazione efficiente del PageRank su cluster costituiti da personal computer. L'implementazione analizzata ha infatti evidenziato una scalabilità negativa, il tempo di esecuzione dell'algoritmo aumenta linearmente in funzione del numero di processori. Questi risultati sono stati ottenuti lanciando l'algoritmo del PageRank della Parallel BGL su un cluster di 43 PC dual-core con 2GB di RAM l'uno, usando diversi grafi scelti in modo da facilitare l'identificazione delle variabili che influenzano la scalabilità. Grafi rappresentanti modelli diversi hanno dato risultati differenti, mostrando che c'è una relazione tra il coefficiente di clustering e l'inclinazione della retta che rappresenta il tempo in funzione del numero di processori. Ad esempio, i grafi Erdős–Rényi, aventi un basso coefficiente di clustering, hanno rappresentato il caso peggiore nei test del PageRank, mentre i grafi Small-World, aventi un alto coefficiente di clustering, hanno rappresentato il caso migliore. Anche le dimensioni del grafo hanno mostrato un'influenza sul tempo di esecuzione particolarmente interessante. Infatti, si è mostrato che la relazione tra il numero di nodi e il numero di archi determina il tempo totale.