Controllo ottico automatizzato di circuiti fotonici integrati: Progettazione, realizzazione e valutazione

In this report a new automated optical test for next generation of photonic integrated circuits (PICs) is provided by the test-bed design and assessment. After a briefly analysis of critical problems of actual optical tests, the main test features are defined: automation and flexibility, relaxed alignment procedure, speed up of entire test and data reliability. After studying varied solutions, the test-bed components are defined to be lens array, photo-detector array, and software controller. Each device is studied and calibrated, the spatial resolution, and reliability against interference at the photo-detector array are studied. The software is programmed in order to manage both PIC input, and photo-detector array output as well as data analysis. The test is validated by analysing state-of-art 16 ports PIC: the waveguide location, current versus power, and time-spatial power distribution are measured as well as the optical continuity of an entire path of PIC. Complexity, alignment tolerance, time of measurement are also discussed.

Novel Machine-Learning Based IC Testing Strategy

The final goal of the thesis should be a real-world application in the production test data environment. This includes the pre-processing of the data, building models and visualizing the results. To do this, different machine learning models, outlier prediction oriented, should be investigated using a real dataset. Finally, the different outlier prediction algorithms should be compared, and their performance discussed.

Non-linear modelling of microwave devices embedding nano-ferroelectric materials for real-time reconfigurable transmitarray

In this thesis work a nonlinear model for Interdigitated Capacitors (IDCs) based on ferroelectric materials, is proposed. Through the properties of materials such as Hafnium-Zirconium Oxide (HfZrO2), it is possible to realize tunable radiofrequency (RF) circuits. In particular, the model proposed in this thesis describes the use of an IDC, realized on a High-Resistivity silicon substrate, as a phase shifter for beam-steering applications. The model is obtained starting from already present experimental measurements, through which it is possible to identify a circuit model. The model is tested for both low power values and other power values using Harmonic Balance simulations, which show an excellent convergence of the model up to 40 dBm of input power. Furthermore, an array composed by two patches operating both at 2.55 GHz, which exploits the tunable properties of the HfZrO-based IDC is proposed. At 0dBm the model shows a 47° phase shift with polarization -1 V and 1 V which leads to a 11° steering of the main lobe of the array.

Energy consumption of parallel algorithms for solving linear systems on HPC architecture

Modern High-Performance Computing HPC systems are gradually increasing in size and complexity due to the correspondent demand of larger simulations requiring more complicated tasks and higher accuracy. However, as side effects of the Dennard’s scaling approaching its ultimate power limit, the efficiency of software plays also an important role in increasing the overall performance of a computation. Tools to measure application performance in these increasingly complex environments provide insights into the intricate ways in which software and hardware interact. The monitoring of the power consumption in order to save energy is possible through processors interfaces like Intel Running Average Power Limit RAPL. Given the low level of these interfaces, they are often paired with an application-level tool like Performance Application Programming Interface PAPI. Since several problems in many heterogeneous fields can be represented as a complex linear system, an optimized and scalable linear system solver algorithm can decrease significantly the time spent to compute its resolution. One of the most widely used algorithms deployed for the resolution of large simulation is the Gaussian Elimination, which has its most popular implementation for HPC systems in the Scalable Linear Algebra PACKage ScaLAPACK library. However, another relevant algorithm, which is increasing in popularity in the academic field, is the Inhibition Method. This thesis compares the energy consumption of the Inhibition Method and Gaussian Elimination from ScaLAPACK to profile their execution during the resolution of linear systems above the HPC architecture offered by CINECA. Moreover, it also collates the energy and power values for different ranks, nodes, and sockets configurations. The monitoring tools employed to track the energy consumption of these algorithms are PAPI and RAPL, that will be integrated with the parallel execution of the algorithms managed with the Message Passing Interface MPI.