Advanced SPM studies on the growth of ultrathin films of organic semiconductors at metal and dielectric interfaces

Many studies on the morphology, molecular orientation, device performance, substrate nature and growth parameter dependence have been carried out since the proposal of Sexithiophene (6T) for organic electronics [ ] However, these studies were mostly performed on films thicker than 20nm and without specifically addressing the relationship between morphology and molecular orientation within the nano and micro structures of ultrathin films of 0-3 monolayers. In 2004, the observation that in OFETs only the first few monolayers at the interface in contact with the gate insulator contribute to the charge transport [ ], underlined the importance to study submonolayer films and their evolution up to a few monolayers of thickness with appropriate experimental techniques. We present here a detailed Non-contact Atomic Force Microscopy and Scanning Tunneling Microscopy study on various substrates aiming at the investigation of growth mechanisms. Most reported similar studies are performed on ideal metals in UHV. However it is important to investigate the details of organic film growth on less ideal and even technological surfaces and device testpatterns. The present work addresses the growth of ultra thin organic films in-situ and quasi real-time by NC-AFM. An organic effusion cell is installed to evaporate the organic material directly onto the SPM sample scanning stage.

Studies on the dual in Mycenaean, in the Homeric poetry and in the Attic Theatre of the 5th century — morphological, dialectal and stylistical variations

The present dissertation focuses on the dual number in Ancient Greek in a diachronical lapse stretching from the Mycenaean age to the Attic Drama and Comedy of the 5th century BC. In the first chapter morphological issues are addressed, chiefly in a comparative perspective. The Indo European evidence on the dual is hence gathered in order to sketch patterns of grammaticalisation and paradigmatisation of specific grams, growing increasingly functional within the Greek domain. In the second chapter syntactical problems are tackled. After a survey of scholarly literature on the Greek dual, we engage in a functional and typological approach, in order to disentangle some biased assessments on the dual, namely its alleged lack of regularity and intermittent agreement. Some recent frameworks in General Linguistics provide useful grounds for casting new light on the subject. Internal Reconstruction, for instance, supports the facultativity of the dual in each and every stage of its development; Typology and the Animacy Hierarcy add precious cross linguistical insight on the behaviour of the dual toward agreement. Glaring differences also arise as to the adoption — or avoidance — of the dual by different authors. Idiolectal varieties prove in fact conditioned by stylistical and register necessity. By means of a comparison among Epics, Tragedy and Comedy it is possible to enhance differences in the evaluation of the dual, which led sometimes to forms of ‘censure’ — thus triggering the onset of competing strategies to express duality. The last two chapters delve into the tantalising variety of the Homeric evidence, first of all in an account of the notorious issue of the Embassy of Iliad IX, and last in a commentary of all significant Homeric duals — mostly represented by archaisms, formulae, and ad hoc coinages.

Methodologies for Synthesizable Programmable Devices based on Multi-Stage Switching Networks

Nowadays the rise of non-recurring engineering (NRE) costs associated with complexity is becoming a major factor in SoC design, limiting both scaling opportunities and the flexibility advantages offered by the integration of complex computational units. The introduction of embedded programmable elements can represent an appealing solution, able both to guarantee the desired flexibility and upgradabilty and to widen the SoC market. In particular embedded FPGA (eFPGA) cores can provide bit-level optimization for those applications which benefits from synthesis, paying on the other side in terms of performance penalties and area overhead with respect to standard cell ASIC implementations. In this scenario this thesis proposes a design methodology for a synthesizable programmable device designed to be embedded in a SoC. A soft-core embedded FPGA (eFPGA) is hence presented and analyzed in terms of the opportunities given by a fully synthesizable approach, following an implementation flow based on Standard-Cell methodology. A key point of the proposed eFPGA template is that it adopts a Multi-Stage Switching Network (MSSN) as the foundation of the programmable interconnects, since it can be efficiently synthesized and optimized through a standard cell based implementation flow, ensuring at the same time an intrinsic congestion-free network topology. The evaluation of the flexibility potentialities of the eFPGA has been performed using different technology libraries (STMicroelectronics CMOS 65nm and BCD9s 0.11μm) through a design space exploration in terms of area-speed-leakage tradeoffs, enabled by the full synthesizability of the template. Since the most relevant disadvantage of the adopted soft approach, compared to a hardcore, is represented by a performance overhead increase, the eFPGA analysis has been made targeting small area budgets. The generation of the configuration bitstream has been obtained thanks to the implementation of a custom CAD flow environment, and has allowed functional verification and performance evaluation through an application-aware analysis.