Modelling and analysis of networked control strategies in smart power distribution grids: development of co-simulation tools

This thesis is focused on Smart Grid applications in medium voltage distribution networks. For the development of new applications it appears useful the availability of simulation tools able to model dynamic behavior of both the power system and the communication network. Such a co-simulation environment would allow the assessment of the feasibility of using a given network technology to support communication-based Smart Grid control schemes on an existing segment of the electrical grid and to determine the range of control schemes that different communications technologies can support. For this reason, is presented a co-simulation platform that has been built by linking the Electromagnetic Transients Program Simulator (EMTP v3.0) with a Telecommunication Network Simulator (OPNET-Riverbed v18.0). The simulator is used to design and analyze a coordinate use of Distributed Energy Resources (DERs) for the voltage/var control (VVC) in distribution network. This thesis is focused control structure based on the use of phase measurement units (PMUs). In order to limit the required reinforcements of the communication infrastructures currently adopted by Distribution Network Operators (DNOs), the study is focused on leader-less MAS schemes that do not assign special coordinating rules to specific agents. Leader-less MAS are expected to produce more uniform communication traffic than centralized approaches that include a moderator agent. Moreover, leader-less MAS are expected to be less affected by limitations and constraint of some communication links. The developed co-simulator has allowed the definition of specific countermeasures against the limitations of the communication network, with particular reference to the latency and loss and information, for both the case of wired and wireless communication networks. Moreover, the co-simulation platform has bee also coupled with a mobility simulator in order to study specific countermeasures against the negative effects on the medium voltage/current distribution network caused by the concurrent connection of electric vehicles.

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

Reti sociali e realtà aumentata: la digitalizzazione della vita quotidiana

Il mio progetto di ricerca è nato da una riflessione concernente una domanda fondamentale che si pongono gli studiosi della comunicazione digitale: le attuali tecnologie mediali che hanno creato nuovi modelli comunicativi e inaugurato inedite modalità di interrelazione sociale conducono a un dualismo digitale o a una realtà aumentata? Si è cercato di dare una risposta a questo interrogativo attraverso un’indagine compiuta su un social network, Facebook, che è la piattaforma digitale più diffusa nel mondo. L’analisi su Facebook, è stata preceduta da una riflessione sui concetti dello spazio e del tempo elaborati dalla letteratura filosofica e sociologica. Tale riflessione è stata propedeutica all’analisi volta a cogliere l’impatto che hanno avuto sulla relazionalità intersoggettiva e sulle dinamiche di realizzazione del sé l’interazione semantica nello spazio delimitato della piazza tradizionale, la molteplicità e la potenza seduttiva delle offerte comunicative dei media elettronici nella estensione della piazza massmediale e soprattutto la nascita e l’affermazione del cyberspazio come luogo della comunicazione nella piazza digitale. Se la peculiarità della piazza tradizionale è nel farsi dei rapporti face to face e quella della piazza massmediale nella funzione rilevante della fonte rispetto al destinatario, la caratteristica della piazza digitale consiste nella creazione autonoma di un orizzonte inclusivo che comprende ogni soggetto che si collega con la rete il quale, all’interno del network, riveste il doppio ruolo di consumatore e di produttore di messaggi. Con l’avvento dell’online nella prassi della relazionalità sociale si producono e si attuano due piani di interazioni comunicative, uno relativo all’online e l’altro relativo all’offline. L’ipotesi di lavoro che è stata guida della mia ricerca è che la pervasività dell’online conduca all’integrazione dei due segmenti comunicativi: l’esperienza della comunicazione digitale si inserisce nella prassi sociale quotidiana arricchendo i rapporti semantici propri della relazione face to face e influenzandoli profondamente.

Grid Connected Doubly Fed Induction Generator Based Wind Turbine under LVRT

This project concentrates on the Low Voltage Ride Through (LVRT) capability of Doubly Fed Induction Generator (DFIG) wind turbine. The main attention in the project is, therefore, drawn to the control of the DFIG wind turbine and of its power converter and to the ability to protect itself without disconnection during grid faults. It provides also an overview on the interaction between variable speed DFIG wind turbines and the power system subjected to disturbances, such as short circuit faults. The dynamic model of DFIG wind turbine includes models for both mechanical components as well as for all electrical components, controllers and for the protection device of DFIG necessary during grid faults. The viewpoint of this project is to carry out different simulations to provide insight and understanding of the grid fault impact on both DFIG wind turbines and on the power system itself. The dynamic behavior of DFIG wind turbines during grid faults is simulated and assessed by using a transmission power system generic model developed and delivered by Transmission System Operator in the power system simulation toolbox Digsilent, Matlab/Simulink and PLECS.