3 resultados para power compensation
em AMS Tesi di Dottorato - Alm@DL - Università di Bologna
Resumo:
This dissertation analyzes the effect of market analysts’ expectations of share prices (price targets) on executive compensation. It examines how well the estimated effects of price targets on compensation fit with two competing views on determining executive compensation: the arm’s length bargaining model, which assumes that a board seeks to maximize shareholders’ interests, and the managerial power model, which assumes that a board seeks to maximize managers’ compensation (Bebchuk et al. 2005). The first chapter documents the pattern of CEO pay from fiscal year 1996 to 2010. The second chapter analyzes the Institutional Broker Estimate System Detail History Price Target data file, which that reports analysts’ price targets for firms. I show that the number of price target announcements is positively associated with company share price’s volatility, that price targets are predictive of changes in the value of stocks, and that when analysts announce positive (negative) expectations of future stock price, share prices change in the same direction in the short run. The third chapter analyzes the effect of price targets on executive compensation. I find that analysts' price targets alter the composition of executive pay between cash-based compensation and stock-based compensation. When analysts forecast a rise (fall) in the share price for a firm, the compensation package tilts toward stock-based (cash-based) compensation. The substitution effect is stronger in companies that have weaker corporate governance. The fourth chapter explores the effect of the introduction of the Sarbanes-Oxley Act (SOX) in 2002 and its reinforcement in 2006 on the options granting process. I show that the introduction of SOX and its reinforcement eliminated the practice of backdating options but increased “spring-loading” of option grants around price targets announcements. Overall, the dissertation shows that price targets provide insights into the determinants of executive pay in favor of the managerial power model.
Resumo:
Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.
Resumo:
Wireless Sensor Networks (WSNs) offer a new solution for distributed monitoring, processing and communication. First of all, the stringent energy constraints to which sensing nodes are typically subjected. WSNs are often battery powered and placed where it is not possible to recharge or replace batteries. Energy can be harvested from the external environment but it is a limited resource that must be used efficiently. Energy efficiency is a key requirement for a credible WSNs design. From the power source's perspective, aggressive energy management techniques remain the most effective way to prolong the lifetime of a WSN. A new adaptive algorithm will be presented, which minimizes the consumption of wireless sensor nodes in sleep mode, when the power source has to be regulated using DC-DC converters. Another important aspect addressed is the time synchronisation in WSNs. WSNs are used for real-world applications where physical time plays an important role. An innovative low-overhead synchronisation approach will be presented, based on a Temperature Compensation Algorithm (TCA). The last aspect addressed is related to self-powered WSNs with Energy Harvesting (EH) solutions. Wireless sensor nodes with EH require some form of energy storage, which enables systems to continue operating during periods of insufficient environmental energy. However, the size of the energy storage strongly restricts the use of WSNs with EH in real-world applications. A new approach will be presented, which enables computation to be sustained during intermittent power supply. The discussed approaches will be used for real-world WSN applications. The first presented scenario is related to the experience gathered during an European Project (3ENCULT Project), regarding the design and implementation of an innovative network for monitoring heritage buildings. The second scenario is related to the experience with Telecom Italia, regarding the design of smart energy meters for monitoring the usage of household's appliances.