Excitonic properties of transition metal oxide perovskites and workflow automatization of GW schemes

The Many-Body-Perturbation Theory approach is among the most successful theoretical frameworks for the study of excited state properties. It allows to describe the excitonic interactions, which play a fundamental role in the optical response of insulators and semiconductors. The first part of the thesis focuses on the study of the quasiparticle, optical and excitonic properties of \textit{bulk} Transition Metal Oxide (TMO) perovskites using a G$_0$W$_0$+Bethe Salpeter Equation (BSE) approach. A representative set of 14 compounds has been selected, including 3d, 4d and 5d perovskites. An approximation of the BSE scheme, based on an analytic diagonal expression for the inverse dielectric function, is used to compute the exciton binding energies and is carefully bench-marked against the standard BSE results. In 2019 an important breakthrough has been achieved with the synthesis of ultrathin SrTiO3 films down to the monolayer limit. This allows us to explore how the quasiparticle and optical properties of SrTiO3 evolve from the bulk to the two-dimensional limit. The electronic structure is computed with G0W0 approach: we prove that the inclusion of the off-diagonal self-energy terms is required to avoid non-physical band dispersions. The excitonic properties are investigated beyond the optical limit at finite momenta. Lastly a study of the under pressure optical response of the topological nodal line semimetal ZrSiS is presented, in conjunction with the experimental results from the group of Prof. Dr. Kuntscher of the Augsburg University. The second part of the thesis discusses the implementation of a workflow to automate G$_0$W$_0$ and BSE calculations with the VASP software. The workflow adopts a convergence scheme based on an explicit basis-extrapolation approach [J. Klimeš \textit{et al.}, Phys. Rev.B 90, 075125 (2014)] which allows to reduce the number of intermediate calculations required to reach convergence and to explicit estimate the error associated to the basis-set truncation.

Nanostructured piezoelectric materials for the design and development of self-sensing composite materials and energy harvesting devices

The work activities reported in this PhD thesis regard the functionalization of composite materials and the realization of energy harvesting devices by using nanostructured piezoelectric materials, which can be integrated in the composite without affecting its mechanical properties. The self-sensing composite materials were fabricated by interleaving between the plies of the laminate the piezoelectric elements. The problem of negatively impacting on the mechanical properties of the hosting structure was addressed by shaping the piezoelectric materials in appropriate ways. In the case of polymeric piezoelectric materials, the electrospinning technique allowed to produce highly-porous nanofibrous membranes which can be immerged in the hosting matrix without inducing delamination risk. The flexibility of the polymers was exploited also for the production of flexible tactile sensors. The sensing performances of the specimens were evaluated also in terms of lifetime with fatigue tests. In the case of ceramic piezo-materials, the production and the interleaving of nanometric piezoelectric powder limitedly affected the impact resistance of the laminate, which showed enhanced sensing properties. In addition to this, a model was proposed to predict the piezoelectric response of the self-sensing composite materials as function of the amount of the piezo-phase within the laminate and to adapt its sensing functionalities also for quasi-static loads. Indeed, one final application of the work was to integrate the piezoelectric nanofibers in the sole of a prosthetic foot in order to detect the walking cycle, which has a period in the order of 1 second. In the end, the energy harvesting capabilities of the piezoelectric materials were investigated, with the aim to design wearable devices able to collect energy from the environment and from the body movements. The research activities focused both on the power transfer capability to an external load and the charging of an energy storage unit, like, e.g., a supercapacitor.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Temperature Variation Aware Energy Optimization in Heterogeneous MPSoCs

Thermal effects are rapidly gaining importance in nanometer heterogeneous integrated systems. Increased power density, coupled with spatio-temporal variability of chip workload, cause lateral and vertical temperature non-uniformities (variations) in the chip structure. The assumption of an uniform temperature for a large circuit leads to inaccurate determination of key design parameters. To improve design quality, we need precise estimation of temperature at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis of the designs needs to be done at multiple levels of granularity. To further investigate the flow of chip/package thermal analysis we exploit the Intel Single Chip Cloud Computer (SCC) and propose a methodology for calibration of SCC on-die temperature sensors. We also develop an infrastructure for online monitoring of SCC temperature sensor readings and SCC power consumption. Having the thermal simulation tool in hand, we propose MiMAPT, an approach for analyzing delay, power and temperature in digital integrated circuits. MiMAPT integrates seamlessly into industrial Front-end and Back-end chip design flows. It accounts for temperature non-uniformities and self-heating while performing analysis. Furthermore, we extend the temperature variation aware analysis of designs to 3D MPSoCs with Wide-I/O DRAM. We improve the DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting the per-DRAM-bank refresh period accordingly. We develop an advanced virtual platform which models the performance, power, and thermal behavior of a 3D-integrated MPSoC with Wide-I/O DRAMs in detail. Moving towards real-world multi-core heterogeneous SoC designs, a reconfigurable heterogeneous platform (ZYNQ) is exploited to further study the performance and energy efficiency of various CPU-accelerator data sharing methods in heterogeneous hardware architectures. A complete hardware accelerator featuring clusters of OpenRISC CPUs, with dynamic address remapping capability is built and verified on a real hardware.