Interconnection systems for highly integrated computation devices

The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the on-chip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation focuses on all of the above points, by describing a NoC architectural implementation called ×pipes; a NoC simulation environment within a cycle-accurate MPSoC emulator called MPARM; a NoC design flow consisting of a front-end tool for optimal NoC instantiation, called SunFloor, and a set of back-end facilities for the study of NoC physical implementations. This dissertation proves the viability of NoCs for current and upcoming designs, by outlining their advantages (alongwith a fewtradeoffs) and by providing a full NoC implementation framework. It also presents some examples of additional extensions of NoCs, allowing e.g. for increased fault tolerance, and outlines where NoCsmay find further application scenarios, such as in stacked chips.

Longterm peripheral baroreflex and chemoreflex function after bilateral eversion carotid endarterectomy

Introduction The “eversion” technique for carotid endarterectomy (e-CEA), that involves the transection of the internal carotid artery at the carotid bulb and its eversion over the atherosclerotic plaque, has been associated with an increased risk of postoperative hypertension possibly due to a direct iatrogenic damage to the carotid sinus fibers. The aim of this study is to assess the long-term effect of the e-CEA on arterial baroreflex and peripheral chemoreflex function in humans. Methods A retrospective review was conducted on a prospectively compiled computerized database of 3128 CEAs performed on 2617 patients at our Center between January 2001 and March 2006. During this period, a total of 292 patients who had bilateral carotid stenosis ≥70% at the time of the first admission underwent staged bilateral CEAs. Of these, 93 patients had staged bilateral e-CEAs, 126 staged bilateral s- CEAs and 73 had different procedures on each carotid. CEAs were performed with either the eversion or the standard technique with routine Dacron patching in all cases. The study inclusion criteria were bilateral CEA with the same technique on both sides and an uneventful postoperative course after both procedures. We decided to enroll patients submitted to bilateral e-CEA to eliminate the background noise from contralateral carotid sinus fibers. Exclusion criteria were: age >70 years, diabetes mellitus, chronic pulmonary disease, symptomatic ischemic cardiac disease or medical therapy with b-blockers, cardiac arrhythmia, permanent neurologic deficits or an abnormal preoperative cerebral CT scan, carotid restenosis and previous neck or chest surgery or irradiation. Young and aged-matched healthy subjects were also recruited as controls. Patients were assessed by the 4 standard cardiovascular reflex tests, including Lying-to-standing, Orthostatic hypotension, Deep breathing, and Valsalva Maneuver. Indirect autonomic parameters were assessed with a non-invasive approach based on spectral analysis of EKG RR interval, systolic arterial pressure, and respiration variability, performed with an ad hoc software. From the analysis of these parameters the software provides the estimates of spontaneous baroreflex sensitivity (BRS). The ventilatory response to hypoxia was assessed in patients and controls by means of classic rebreathing tests. Results A total of 29 patients (16 males, age 62.4±8.0 years) were enrolled. Overall, 13 patients had undergone bilateral e-CEA (44.8%) and 16 bilateral s-CEA (55.2%) with a mean interval between the procedures of 62±56 days. No patient showed signs or symptoms of autonomic dysfunction, including labile hypertension, tachycardia, palpitations, headache, inappropriate diaphoresis, pallor or flushing. The results of standard cardiovascular autonomic tests showed no evidence of autonomic dysfunction in any of the enrolled patients. At spectral analysis, a residual baroreflex performance was shown in both patient groups, though reduced, as expected, compared to young controls. Notably, baroreflex function was better maintained in e-CEA, compared to standard CEA. (BRS at rest: young controls 19.93 ± 2.45 msec/mmHg; age-matched controls 7.75 ± 1.24; e-CEA 13.85 ± 5.14; s-CEA 4.93 ± 1.15; ANOVA P=0.001; BRS at stand: young controls 7.83 ± 0.66; age-matched controls 3.71 ± 0.35; e-CEA 7.04 ± 1.99; s-CEA 3.57 ± 1.20; ANOVA P=0.001). In all subjects ventilation (VÝ E) and oximetry data fitted a linear regression model with r values > 0.8. Oneway analysis of variance showed a significantly higher slope both for ΔVE/ΔSaO2 in controls compared with both patient groups which were not different from each other (-1.37 ± 0.33 compared with -0.33±0.08 and -0.29 ±0.13 l/min/%SaO2, p<0.05, Fig.). Similar results were observed for and ΔVE/ΔPetO2 (-0.20 ± 0.1 versus -0.01 ± 0.0 and -0.07 ± 0.02 l/min/mmHg, p<0.05). A regression model using treatment, age, baseline FiCO2 and minimum SaO2 achieved showed only treatment as a significant factor in explaining the variance in minute ventilation (R2= 25%). Conclusions Overall, we demonstrated that bilateral e-CEA does not imply a carotid sinus denervation. As a result of some expected degree of iatrogenic damage, such performance was lower than that of controls. Interestingly though, baroreflex performance appeared better maintained in e-CEA than in s-CEA. This may be related to the changes in the elastic properties of the carotid sinus vascular wall, as the patch is more rigid than the endarterectomized carotid wall that remains in the e-CEA. These data confirmed the safety of CEA irrespective of the surgical technique and have relevant clinical implication in the assessment of the frequent hemodynamic disturbances associated with carotid angioplasty stenting.

Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS

Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.