I Fondi Strutturali europei 2007-2013 in Italia: un'analisi delle criticità

A 7 anni dall’avvio dell’ attuazione della Politica di Coesione dell’Unione Europea 2007- 2013, l’Italia ha il tasso di assorbimento dei Fondi Strutturali più basso d’Europa, insieme alla Romania, e rischia di subire un disimpegno delle risorse, che rappresenterebbe un gravissimo fallimento economico e politico. Il contributo di questo lavoro al dibattito sull’uso dei Fondi strutturali in Italia è duplice. Da una parte, per la prima volta, si propone uno studio sistematico delle criticità nella gestione del periodo 2007-2013, che hanno causato l’attuale ritardo nella spesa. Dall’altra, si affronta il problema italiano sia da una prospettiva europea sia nella sua dimensione nazionale, indagando le differenze regionali nella performance di spesa e proponendo un’analisi basata su tre dimensioni principali delle criticità: finanziaria, politica, amministrativa. L’approccio della ricerca consiste nella convergenza di dati quantitativi e qualitativi, raccolti durante un periodo di ricerca a Bruxelles e presso le Autorità di Gestione dei Programmi Operativi cofinanziati dal FESR. La questione dell’assorbimento finanziario e del ritardo nell’attuazione è stata indagata da tre punti di vista. Una prospettiva “storica”, che ha raccontato il ritardo strutturale nell’utilizzo dei Fondi Strutturali in Italia e che ha chiarito come il problema italiano, prima dell’attuale ciclo 2007-2013, sia stato non di quantità, ma di qualità della spesa. La seconda prospettiva è stata di respiro europeo, ed è servita a indagare le cause del basso livello di assorbimento finanziario dell’Italia suggerendo alcuni elementi utili a comprendere le ragioni di un simile divario con gli altri Paesi. Infine, la prospettiva nazionale e regionale ha svelato l’esistenza di un mix complesso, e micidiale, che ha letteralmente paralizzato la spesa italiana dei Fondi. Un mix di fattori finanziari, politici e amministrativi che non ha avuto eguali negli altri Paesi, e che si è concentrato soprattutto, ma non esclusivamente, nelle regioni dell’Obiettivo Convergenza.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.