Studio di popolazione sull'associazione tra sindrome delle gambe senza riposo ed emicrania

Introduzione: La sindrome delle gambe senza riposo (RLS) è un disturbo caratterizzato da sensazione spiacevole disestesica generalmente agli arti inferiori, che si presenta o peggiora nelle ore serali-notturne e che migliora con il movimento. Studi clinici hanno mostrato una maggiore prevalenza di RLS negli emicranici, mentre mancano studi condotti su popolazione generale non selezionata. Lo scopo di questo studio era quello di valutare la associazione tra emicrania e RLS in una popolazione italiana adulta. Inoltre è stata valutata l’associazione tra RLS e cefalea fenotipizzata attraverso metodica di principal components analysis (PCA). Materiali e metodi: la presenza di RLS e di emicrania è stata determinata attraverso questionari basati sui criteri diagnostici correnti in un campione di 1567 partecipanti di un fase preliminare di uno studio in corso sulla popolazione adulta della Val Venosta (BZ). Risultati: gli emicranici hanno presentato un significativo maggior rischio di soffrire di RLS rispetto ai non emicranici, anche dopo aggiustamento per fattori confondenti come età, sesso, depressione, ansia e qualità del sonno (p = 0.049). Questa associazione non era modificata dalla presenza di aura emicranica, di cause possibili di RLS secondaria e dalla frequenza di attacchi emicranici. Inoltre la RLS non era risultata significativamente associata alla cefalea di tipo tensivo (TTH). Dall’analisi di associazione tra RLS e cefalea fenotipizzata attraverso PCA era emerso che la componente 1, caratterizzata da sintomi di sensitivizzazione del sistema nervoso centrale (SNC), correlava significativamente con la presenza di RLS (p = 0.021). Conclusioni: RLS ed emicrania sono risultate associate nel nostro campione di popolazione adulta; inoltre la RLS ha mostrato una correlazione significativa con i sintomi di sensitivizzazione del SNC legati agli attacchi di cefalea. Questa associazione potrebbe risiedere in una possibile base patogenetica comune.

An Input-Process-Output Approach to Interorganizational Teams: The Influence of Work Group Diversity, Trust and Shared Leadership on Communication Network and Team Outputs.

The market’s challenges bring firms to collaborate with other organizations in order to create Joint Ventures, Alliances and Consortia that are defined as “Interorganizational Networks” (IONs) (Provan, Fish and Sydow; 2007). Some of these IONs are managed through a shared partecipant governance (Provan and Kenis, 2008): a team composed by entrepreneurs and/or directors of each firm of an ION. The research is focused on these kind of management teams and it is based on an input-process-output model: some input variables (work group’s diversity, intra-team's friendship network density) have a direct influence on the process (team identification, shared leadership, interorganizational trust, team trust and intra-team's communication network density), which influence some team outputs, individual innovation behaviors and team effectiveness (team performance, work group satisfaction and ION affective commitment). Data was collected on a sample of 101 entrepreneurs grouped in 28 ION’s government teams and the research hypotheses are tested trough the path analysis and the multilevel models. As expected trust in team and shared leadership are positively and directly related to team effectiveness while team identification and interorganizational trust are indirectly related to the team outputs. The friendship network density among the team’s members has got positive effects on the trust in team and on the communication network density, and also, through the communication network density it improves the level of the teammates ION affective commitment. The shared leadership and its effects on the team effectiveness are fostered from higher level of team identification and weakened from higher level of work group diversity, specifically gender diversity. Finally, the communication network density and shared leadership at the individual level are related to the frequency of individual innovative behaviors. The dissertation’s results give a wider and more precise indication about the management of interfirm network through “shared” form of governance.

Use of shared memory in the context of embedded multi-core processors: exploration of the technology and its limits

Modern embedded systems embrace many-core shared-memory designs. Due to constrained power and area budgets, most of them feature software-managed scratchpad memories instead of data caches to increase the data locality. It is therefore programmers’ responsibility to explicitly manage the memory transfers, and this make programming these platform cumbersome. Moreover, complex modern applications must be adequately parallelized before they can the parallel potential of the platform into actual performance. To support this, programming languages were proposed, which work at a high level of abstraction, and rely on a runtime whose cost hinders performance, especially in embedded systems, where resources and power budget are constrained. This dissertation explores the applicability of the shared-memory paradigm on modern many-core systems, focusing on the ease-of-programming. It focuses on OpenMP, the de-facto standard for shared memory programming. In a first part, the cost of algorithms for synchronization and data partitioning are analyzed, and they are adapted to modern embedded many-cores. Then, the original design of an OpenMP runtime library is presented, which supports complex forms of parallelism such as multi-level and irregular parallelism. In the second part of the thesis, the focus is on heterogeneous systems, where hardware accelerators are coupled to (many-)cores to implement key functional kernels with orders-of-magnitude of speedup and energy efficiency compared to the “pure software” version. However, three main issues rise, namely i) platform design complexity, ii) architectural scalability and iii) programmability. To tackle them, a template for a generic hardware processing unit (HWPU) is proposed, which share the memory banks with cores, and the template for a scalable architecture is shown, which integrates them through the shared-memory system. Then, a full software stack and toolchain are developed to support platform design and to let programmers exploiting the accelerators of the platform. The OpenMP frontend is extended to interact with it.