Tecniche per il controllo dinamico del consumo di potenza per piattaforme system-on-chip

Providing support for multimedia applications on low-power mobile devices remains a significant research challenge. This is primarily due to two reasons: • Portable mobile devices have modest sizes and weights, and therefore inadequate resources, low CPU processing power, reduced display capabilities, limited memory and battery lifetimes as compared to desktop and laptop systems. • On the other hand, multimedia applications tend to have distinctive QoS and processing requirementswhichmake themextremely resource-demanding. This innate conflict introduces key research challenges in the design of multimedia applications and device-level power optimization. Energy efficiency in this kind of platforms can be achieved only via a synergistic hardware and software approach. In fact, while System-on-Chips are more and more programmable thus providing functional flexibility, hardwareonly power reduction techniques cannot maintain consumption under acceptable bounds. It is well understood both in research and industry that system configuration andmanagement cannot be controlled efficiently only relying on low-level firmware and hardware drivers. In fact, at this level there is lack of information about user application activity and consequently about the impact of power management decision on QoS. Even though operating system support and integration is a requirement for effective performance and energy management, more effective and QoSsensitive power management is possible if power awareness and hardware configuration control strategies are tightly integratedwith domain-specificmiddleware services. The main objective of this PhD research has been the exploration and the integration of amiddleware-centric energymanagement with applications and operating-system. We choose to focus on the CPU-memory and the video subsystems, since they are the most power-hungry components of an embedded system. A second main objective has been the definition and implementation of software facilities (like toolkits, API, and run-time engines) in order to improve programmability and performance efficiency of such platforms. Enhancing energy efficiency and programmability ofmodernMulti-Processor System-on-Chips (MPSoCs) Consumer applications are characterized by tight time-to-market constraints and extreme cost sensitivity. The software that runs on modern embedded systems must be high performance, real time, and even more important low power. Although much progress has been made on these problems, much remains to be done. Multi-processor System-on-Chip (MPSoC) are increasingly popular platforms for high performance embedded applications. This leads to interesting challenges in software development since efficient software development is a major issue for MPSoc designers. An important step in deploying applications on multiprocessors is to allocate and schedule concurrent tasks to the processing and communication resources of the platform. The problem of allocating and scheduling precedenceconstrained tasks on processors in a distributed real-time system is NP-hard. There is a clear need for deployment technology that addresses thesemulti processing issues. This problem can be tackled by means of specific middleware which takes care of allocating and scheduling tasks on the different processing elements and which tries also to optimize the power consumption of the entire multiprocessor platform. This dissertation is an attempt to develop insight into efficient, flexible and optimalmethods for allocating and scheduling concurrent applications tomultiprocessor architectures. It is a well-known problem in literature: this kind of optimization problems are very complex even in much simplified variants, therefore most authors propose simplified models and heuristic approaches to solve it in reasonable time. Model simplification is often achieved by abstracting away platform implementation ”details”. As a result, optimization problems become more tractable, even reaching polynomial time complexity. Unfortunately, this approach creates an abstraction gap between the optimization model and the real HW-SW platform. The main issue with heuristic or, more in general, with incomplete search is that they introduce an optimality gap of unknown size. They provide very limited or no information on the distance between the best computed solution and the optimal one. The goal of this work is to address both abstraction and optimality gaps, formulating accurate models which accounts for a number of ”non-idealities” in real-life hardware platforms, developing novel mapping algorithms that deterministically find optimal solutions, and implementing software infrastructures required by developers to deploy applications for the targetMPSoC platforms. Energy Efficient LCDBacklightAutoregulation on Real-LifeMultimediaAp- plication Processor Despite the ever increasing advances in Liquid Crystal Display’s (LCD) technology, their power consumption is still one of the major limitations to the battery life of mobile appliances such as smart phones, portable media players, gaming and navigation devices. There is a clear trend towards the increase of LCD size to exploit the multimedia capabilities of portable devices that can receive and render high definition video and pictures. Multimedia applications running on these devices require LCD screen sizes of 2.2 to 3.5 inches andmore to display video sequences and pictures with the required quality. LCD power consumption is dependent on the backlight and pixel matrix driving circuits and is typically proportional to the panel area. As a result, the contribution is also likely to be considerable in future mobile appliances. To address this issue, companies are proposing low power technologies suitable for mobile applications supporting low power states and image control techniques. On the research side, several power saving schemes and algorithms can be found in literature. Some of them exploit software-only techniques to change the image content to reduce the power associated with the crystal polarization, some others are aimed at decreasing the backlight level while compensating the luminance reduction by compensating the user perceived quality degradation using pixel-by-pixel image processing algorithms. The major limitation of these techniques is that they rely on the CPU to perform pixel-based manipulations and their impact on CPU utilization and power consumption has not been assessed. This PhDdissertation shows an alternative approach that exploits in a smart and efficient way the hardware image processing unit almost integrated in every current multimedia application processors to implement a hardware assisted image compensation that allows dynamic scaling of the backlight with a negligible impact on QoS. The proposed approach overcomes CPU-intensive techniques by saving system power without requiring either a dedicated display technology or hardware modification. Thesis Overview The remainder of the thesis is organized as follows. The first part is focused on enhancing energy efficiency and programmability of modern Multi-Processor System-on-Chips (MPSoCs). Chapter 2 gives an overview about architectural trends in embedded systems, illustrating the principal features of new technologies and the key challenges still open. Chapter 3 presents a QoS-driven methodology for optimal allocation and frequency selection for MPSoCs. The methodology is based on functional simulation and full system power estimation. Chapter 4 targets allocation and scheduling of pipelined stream-oriented applications on top of distributed memory architectures with messaging support. We tackled the complexity of the problem by means of decomposition and no-good generation, and prove the increased computational efficiency of this approach with respect to traditional ones. Chapter 5 presents a cooperative framework to solve the allocation, scheduling and voltage/frequency selection problem to optimality for energyefficient MPSoCs, while in Chapter 6 applications with conditional task graph are taken into account. Finally Chapter 7 proposes a complete framework, called Cellflow, to help programmers in efficient software implementation on a real architecture, the Cell Broadband Engine processor. The second part is focused on energy efficient software techniques for LCD displays. Chapter 8 gives an overview about portable device display technologies, illustrating the principal features of LCD video systems and the key challenges still open. Chapter 9 shows several energy efficient software techniques present in literature, while Chapter 10 illustrates in details our method for saving significant power in an LCD panel. Finally, conclusions are drawn, reporting the main research contributions that have been discussed throughout this dissertation.

Laser cladding and its potential to reduce particulate matter emissions from the automotive and locomotive sector

Laser Cladding (LC) is an emerging technology which is used both for coating applications as well as near-net shape fabrication. Despite its significant advantages, such as low dilution and metallurgical bond with the substrate, it still faces issues such as process control and repeatability, which restricts the extension to its applications. The following thesis evaluates the LC technology and tests its potential to be applied to reduce particulate matter emissions from the automotive and locomotive sector. The evaluation of LC technology was carried out for the deposition of multi-layer and multi-track coatings. 316L stainless steel coatings were deposited to study the minimisation of geometric distortions in thin-walled samples. Laser power, as well as scan strategy, were the main variables to achieve this goal. The use of constant power, reduction at successive layers, a control loop control system, and two different scan strategies were studied. The closed-loop control system was found to be practical only when coupled with the correct scan strategy for the deposition of thin walls. Three overlapped layers of aluminium bronze were deposited onto a structural steel pipe for multitrack coatings. The effect of laser power, scan speed and hatch distance on the final geometry of coating were studied independently, and a combined parameter was established to effectively control each geometrical characteristic (clad width, clad height and percentage of dilution). LC was then applied to coat commercial GCI brake discs with tool steel. The optical micrography showed that even with preheating, the cracks that originated from the substrate towards the coating were still present. The commercial brake discs emitted airborne particles whose concentration and size depended on the test conditions used for simulation in the laboratory. The contact of LC cladded wheel with rail emitted significantly less ultra-fine particles while maintaining the acceptable values of coefficient of friction.

Ultra-low power WSNs: distributed signal processing and dynamic resource management

This thesis presents several data processing and compression techniques capable of addressing the strict requirements of wireless sensor networks. After introducing a general overview of sensor networks, the energy problem is introduced, dividing the different energy reduction approaches according to the different subsystem they try to optimize. To manage the complexity brought by these techniques, a quick overview of the most common middlewares for WSNs is given, describing in detail SPINE2, a framework for data processing in the node environment. The focus is then shifted on the in-network aggregation techniques, used to reduce data sent by the network nodes trying to prolong the network lifetime as long as possible. Among the several techniques, the most promising approach is the Compressive Sensing (CS). To investigate this technique, a practical implementation of the algorithm is compared against a simpler aggregation scheme, deriving a mixed algorithm able to successfully reduce the power consumption. The analysis moves from compression implemented on single nodes to CS for signal ensembles, trying to exploit the correlations among sensors and nodes to improve compression and reconstruction quality. The two main techniques for signal ensembles, Distributed CS (DCS) and Kronecker CS (KCS), are introduced and compared against a common set of data gathered by real deployments. The best trade-off between reconstruction quality and power consumption is then investigated. The usage of CS is also addressed when the signal of interest is sampled at a Sub-Nyquist rate, evaluating the reconstruction performance. Finally the group sparsity CS (GS-CS) is compared to another well-known technique for reconstruction of signals from an highly sub-sampled version. These two frameworks are compared again against a real data-set and an insightful analysis of the trade-off between reconstruction quality and lifetime is given.

Design and characterization of wideband Hall current sensors in BCD technology for smart power and metering applications

Power electronic circuits are moving towards higher switching frequencies, exploiting the capabilities of novel devices to shrink the dimension of passive components. This trend demands sensors capable enough to operate at such high frequencies. This thesis aims to demonstrate through experimental characterization, the broadband capability of a fully integrated CMOS X-Hall current sensor in current mode interfaced with a transimpedance amplifier (TIA), chip CH09, realized in CMOS technology for power electronics applications such as power converters. The system exploits a common-mode control system to operate the dual supply system, 5-V for the X-Hall probe and 1.2-V for the readout. The developed prototype achieves a maximum acquisition bandwidth of 12 MHz, a power consumption of 11.46 mW, resolution of 39 mArms, a sensitivity of 8 % /T, and a FoM of 569-MHz/A2mW, significantly higher than current state-of-the-art. Further enhancements were proposed to CH09 as a new chip CH100, aiming for accuracy levels prerequisite for a real-time power electronic application. The TIA was optimized for a wider bandwidth of 26.7 MHz with nearly 30% reduction of the integrated input referred noise of 26.69 nArms at the probe-AFE interface in the frequency band of DC-30 MHz, and a 10% improvement in the dynamic range. The expected input range is 5-A. The chip incorporates a dual sensing chain for differential sensing to overcome common mode interferences. A novel offset cancellation technique is proposed that would require switching of polarity of bias currents. Thermal gain drift was improved by a factor of 8 and will be digitally calibrated utilizing a new built-in temperature sensor with a post calibration measurement accuracy greater than 1%. The estimated power consumption of the entire system is 55.6 mW. Both prototypes have been implemented through a 90-nm microelectronic process from STMicroelectronics and occupy a silicon area of 2.4 mm2.

Hairpin windings for high reliability and high power density electrical machines

In the last years the increasing demand of higher torque and power densities has led to the adoption of hairpin windings (HWs) in electrical machines, mainly in those intended for automotive applications. However, this winding topology is quite sensitive to AC losses, hence one of their main challenges is represented by their reduction. This work deals with different design aspects related to the enhancements of some performance figures of rotating electrical machines for traction applications, above all power density and reliability, mainly through the adoption of HWs.

Power flow forecasting and smart charging for electric vehicle charging systems with photovoltaic integration

An essential role in the global energy transition is attributed to Electric Vehicles (EVs) the energy for EV traction can be generated by renewable energy sources (RES), also at a local level through distributed power plants, such as photovoltaic (PV) systems. However, EV integration with electrical systems might not be straightforward. The intermittent RES, combined with the high and uncontrolled aggregate EV charging, require an evolution toward new planning and paradigms of energy systems. In this context, this work aims to provide a practical solution for EV charging integration in electrical systems with RES. A method for predicting the power required by an EV fleet at the charging hub (CH) is developed in this thesis. The proposed forecasting method considers the main parameters on which charging demand depends. The results of the EV charging forecasting method are deeply analyzed under different scenarios. To reduce the EV load intermittency, methods for managing the charging power of EVs are proposed. The main target was to provide Charging Management Systems (CMS) that modulate EV charging to optimize specific performance indicators such as system self-consumption, peak load reduction, and PV exploitation. Controlling the EV charging power to achieve specific optimization goals is also known as Smart Charging (SC). The proposed techniques are applied to real-world scenarios demonstrating performance improvements in using SC strategies. A viable alternative to maximize integration with intermittent RES generation is the integration of energy storage. Battery Energy Storage Systems (BESS) may be a buffer between peak load and RES production. A sizing algorithm for PV+BESS integration in EV charging hubs is provided. The sizing optimization aims to optimize the system's energy and economic performance. The results provide an overview of the optimal size that the PV+BESS plant should have to improve whole system performance in different scenarios.

Analysis and improvements of four-wire power converters for electric vehicle chargers

A robust and well-distributed backbone charging network is the priority to ensure widespread electrification of road transport, providing a driving experience similar to that of internal combustion engine vehicles. International standards set multiple technical targets for on-board and off-board electric vehicle chargers; output voltage levels, harmonic emissions, and isolation requirements strongly influence the design of power converters. Additionally, smart-grid services such as vehicle-to-grid and vehicle-to-vehicle require the implementation of bi-directional stages that inevitably increase system complexity and component count. To face these design challenges, the present thesis provides a rigorous analysis of four-leg and split-capacitor three-phase four-wire active front-end topologies focusing on the harmonic description under different modulation techniques and conditions. The resulting analytical formulation paves the way for converter performance improvements while maintaining regulatory constraints and technical requirements under control. Specifically, split-capacitor inverter current ripple was characterized as providing closed-form formulations valid for every sub-case ranging from synchronous to interleaved PWM. Outcomes are the base for a novel variable switching PWM technique capable of mediating harmonic content limitation and switching loss reduction. A similar analysis is proposed for four-leg inverters with a broad range of continuous and discontinuous PWM modulations. The general superiority of discontinuous PWM modulation in reducing switching losses and limiting harmonic emission was demonstrated. Developments are realized through a parametric description of the neutral wire inductor. Finally, a novel class of integrated isolated converter topologies is proposed aiming at the neutral wire delivery without employing extra switching components rather than the one already available in typical three-phase inverter and dual-active-bridge back-to-back configurations. The fourth leg was integrated inside the dual-active-bridge input bridge providing relevant component count savings. A novel modified single-phase-shift modulation technique was developed to ensure a seamless transition between working conditions like voltage level and power factor. Several simulations and experiments validate the outcomes.