Models and Simulations of Diamond-like Carbon for large-area high voltage power diodes

Silicon-based discrete high-power devices need to be designed with optimal performance up to several thousand volts and amperes to reach power ratings ranging from few kWs to beyond the 1 GW mark. To this purpose, a key element is the improvement of the junction termination (JT) since it allows to drastically reduce surface electric field peaks which may lead to an earlier device failure. This thesis will be mostly focused on the negative bevel termination which from several years constitutes a standard processing step in bipolar production lines. A simple methodology to realize its counterpart, a planar JT with variation of the lateral doping concentration (VLD) will be also described. On the JT a thin layer of a semi insulating material is usually deposited, which acts as passivation layer reducing the interface defects and contributing to increase the device reliability. A thorough understanding of how the passivation layer properties affect the breakdown voltage and the leakage current of a fast-recovery diode is fundamental to preserve the ideal termination effect and provide a stable blocking capability. More recently, amorphous carbon, also called diamond-like carbon (DLC), has been used as a robust surface passivation material. By using a commercial TCAD tool, a detailed physical explanation of DLC electrostatic and transport properties has been provided. The proposed approach is able to predict the breakdown voltage and the leakage current of a negative beveled power diode passivated with DLC as confirmed by the successfully validation against the available experiments. In addition, the VLD JT proposed to overcome the limitation of the negative bevel architecture has been simulated showing a breakdown voltage very close to the ideal one with a much smaller area consumption. Finally, the effect of a low junction depth on the formation of current filaments has been analyzed by performing reverse-recovery simulations.

Physical modeling and numerical simulations of degradation mechanisms in devices and insulators for power applications

In this thesis, a TCAD approach for the investigation of charge transport in amorphous silicon dioxide is presented for the first time. The proposed approach is used to investigate high-voltage silicon oxide thick TEOS capacitors embedded in the back-end inter-level dielectric layers for galvanic insulation applications. In the first part of this thesis, a detailed review of the main physical and chemical properties of silicon dioxide and the main physical models for the description of charge transport in insulators are presented. In the second part, the characterization of high-voltage MIM structures at different high-field stress conditions up to the breakdown is presented. The main physical mechanisms responsible of the observed results are then discussed in details. The third part is dedicated to the implementation of a TCAD approach capable of describing charge transport in silicon dioxide layers in order to gain insight into the microscopic physical mechanisms responsible of the leakage current in MIM structures. In particular, I investigated and modeled the role of charge injection at contacts and charge build-up due to trapping and de-trapping mechanisms in the oxide layer to the purpose of understanding its behavior under DC and AC stress conditions. In addition, oxide breakdown due to impact-ionization of carriers has been taken into account in order to have a complete representation of the oxide behavior at very high fields. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach. In the last part of the thesis, the proposed approach has been applied to simulate the breakdown in realistic structures under different stress conditions. The TCAD tool has been used to carry out a detailed analysis of the most relevant physical quantities, in order to gain a detailed understanding on the main mechanisms responsible for breakdown and guide design optimization.