Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

Aspetti di vita quotidiana, religiosa, militare e civile in Britannia e lungo il Vallo di Adriano

The dissertation aims to provide an overview of some aspects of everyday life in Roman Britain in general and in the area of Hadrian’s Wall in particular. In a preliminary description, the writer addresses the complex topic related to the genesis of borders as the fulfillment of the expansionist parable of Rome, and as the space manifestation of the sunset of the idea of an imperium sine fine. Then the thesis passes to examine, in subsequent chapters, first the religious theme in its peculiar indigenous component and in the cultural practices triggered by the process of Romanization, secondly the question whether is possible to study everyday life in the northernmost province of the Empire through a discussion of the civilian settlements in proximity to military sites. This issue is drawn especially thanks to the analysis of the so-called Vindolanda tablets, which constitute a valuable evidence of a lively environment both under human and social respect. Before giving an indication of the specific bibliography, the work offers a number of appendices which elaborate part of the information which has been supplied in the previous sections. Mention of the epigraphic repertoires and literary and antiquarian sources is finally made.

Analysis of the Slow Food movement impact on the farmers and rural areas’ sustainable development

The evaluation of the farmers’ communities’ approach to the Slow Food vision, their perception of the Slow Food role in supporting their activity and their appreciation and expectations from participating in the event of Mother Earth were studied. The Unified Theory of Acceptance and Use of Technology (UTAUT) model was adopted in an agro-food sector context. A survey was conducted, 120 questionnaires from farmers attending the Mother Earth in Turin in 2010 were collected. The descriptive statistical analysis showed that both Slow Food membership and participation to Mother Earth Meeting were much appreciated for the support provided to their business and the contribution to a more sustainable and fair development. A positive social, environmental and psychological impact on farmers also resulted. Results showed also an interesting perspective on the possible universality of the Slow Food and Mother Earth values. Farmers declared that Slow Food is supporting them by preserving the biodiversity and orienting them to the use of local resources and reducing the chemical inputs. Many farmers mentioned the language/culture and administration/bureaucratic issues as an obstacle to be a member in the movement and to participate to the event. Participation to Mother Earth gives an opportunity to exchange information with other farmers’ communities and to participate to seminars and debates, helpful for their business development. The absolute majority of positive answers associated to the farmers’ willingness to relate to Slow Food and participate to the next Mother Earth editions negatively influenced the UTAUT model results. A factor analysis showed that the variables associated to the UTAUT model constructs Performance Expectancy and Effort Expectancy were consistent, able to explain the construct variability, and their measurement reliable. Their inclusion in a simplest Technology Acceptance Model could be considered in future researches.