Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS

Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.

Dry grinding technology for automotive gears manufacturing: process modeling and optimization

The following thesis focused on the dry grinding process modelling and optimization for automotive gears production. A FEM model was implemented with the aim at predicting process temperatures and preventing grinding thermal defects on the material surface. In particular, the model was conceived to facilitate the choice of the grinding parameters during the design and the execution of the dry-hard finishing process developed and patented by the company Samputensili Machine Tools (EMAG Group) on automotive gears. The proposed model allows to analyse the influence of the technological parameters, comprising the grinding wheel specifications. Automotive gears finished by dry-hard finishing process are supposed to reach the same quality target of the gears finished through the conventional wet grinding process with the advantage of reducing production costs and environmental pollution. But, the grinding process allows very high values of specific pressure and heat absorbed by the material, therefore, removing the lubricant increases the risk of thermal defects occurrence. An incorrect design of the process parameters set could cause grinding burns, which affect the mechanical performance of the ground component inevitably. Therefore, a modelling phase of the process could allow to enhance the mechanical characteristics of the components and avoid waste during production. A hierarchical FEM model was implemented to predict dry grinding temperatures and was represented by the interconnection of a microscopic and a macroscopic approach. A microscopic single grain grinding model was linked to a macroscopic thermal model to predict the dry grinding process temperatures and so to forecast the thermal cycle effect caused by the process parameters and the grinding wheel specification choice. Good agreement between the model and the experiments was achieved making the dry-hard finishing an efficient and reliable technology to implement in the gears automotive industry.