Interconnection systems for highly integrated computation devices

The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the on-chip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation focuses on all of the above points, by describing a NoC architectural implementation called ×pipes; a NoC simulation environment within a cycle-accurate MPSoC emulator called MPARM; a NoC design flow consisting of a front-end tool for optimal NoC instantiation, called SunFloor, and a set of back-end facilities for the study of NoC physical implementations. This dissertation proves the viability of NoCs for current and upcoming designs, by outlining their advantages (alongwith a fewtradeoffs) and by providing a full NoC implementation framework. It also presents some examples of additional extensions of NoCs, allowing e.g. for increased fault tolerance, and outlines where NoCsmay find further application scenarios, such as in stacked chips.

Quali-quantitative study of the phenolic and polyphenolic compounds and their antioxidant capacity in vegetal matrix processed with different technologies

Food technologies today mean reducing agricultural food waste, improvement of food security, enhancement of food sensory properties, enlargement of food market and food economies. Food technologists must be high-skilled technicians with good scientific knowledge of food hygiene, food chemistry, industrial technologies and food engineering, sensory evaluation experience and analytical chemistry. Their role is to apply the modern vision of science in the field of human nutrition, rising up knowledge in food science. The present PhD project starts with the aim of studying and improving frozen fruits quality. Freezing process in very powerful in preserve initial raw material characteristics, but pre-treatment before the freezing process are necessary to improve quality, in particular to improve texture and enzymatic activity of frozen foods. Osmotic Dehydration (OD) and Vacuum Impregnation (VI), are useful techniques to modify fruits and vegetables composition and prepare them to freezing process. These techniques permit to introduce cryo-protective agent into the food matrices, without significant changes of the original structure, but cause a slight leaching of important intrinsic compounds. Phenolic and polyphenolic compounds for example in apples and nectarines treated with hypertonic solutions are slightly decreased, but the effect of concentration due to water removal driven out from the osmotic gradient, cause a final content of phenolic compounds similar to that of the raw material. In many experiment, a very important change in fruit composition regard the aroma profile. This occur in strawberries osmo-dehydrated under vacuum condition or under atmospheric pressure condition. The increment of some volatiles, probably due to fermentative metabolism induced by the osmotic stress of hypertonic treatment, induce a sensory profile modification of frozen fruits, that in some way result in a better acceptability of consumer, that prefer treated frozen fruits to untreated frozen fruits. Among different processes used, a very interesting result was obtained with the application of a osmotic pre-treatment driven out at refrigerated temperature for long time. The final quality of frozen strawberries was very high and a peculiar increment of phenolic profile was detected. This interesting phenomenon was probably due to induction of phenolic biological synthesis (for example as reaction to osmotic stress), or to hydrolysis of polymeric phenolic compounds. Aside this investigation in the cryo-stabilization and dehydrofreezing of fruits, deeper investigation in VI techniques were carried out, as studies of changes in vacuum impregnated prickly pear texture, and in use of VI and ultrasound (US) in aroma enrichment of fruit pieces. Moreover, to develop sensory evaluation tools and analytical chemistry determination (of volatiles and phenolic compounds), some researches were bring off and published in these fields. Specifically dealing with off-flavour development during storage of boiled potato, and capillary zonal electrophoresis (CZE) and high performance liquid chromatography (HPLC) determination of phenolic compounds.

Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS

Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.