Interconnection systems for highly integrated computation devices

The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the on-chip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation focuses on all of the above points, by describing a NoC architectural implementation called ×pipes; a NoC simulation environment within a cycle-accurate MPSoC emulator called MPARM; a NoC design flow consisting of a front-end tool for optimal NoC instantiation, called SunFloor, and a set of back-end facilities for the study of NoC physical implementations. This dissertation proves the viability of NoCs for current and upcoming designs, by outlining their advantages (alongwith a fewtradeoffs) and by providing a full NoC implementation framework. It also presents some examples of additional extensions of NoCs, allowing e.g. for increased fault tolerance, and outlines where NoCsmay find further application scenarios, such as in stacked chips.

Architetture di interconnessione per sistemi su singolo chip e per sistemi ad integrazione tridimensionale

I continui sviluppi nel campo della fabbricazione dei circuiti integrati hanno comportato frequenti travolgimenti nel design, nell’implementazione e nella scalabilità dei device elettronici, così come nel modo di utilizzarli. Anche se la legge di Moore ha anticipato e caratterizzato questo trend nelle ultime decadi, essa stessa si trova a fronteggiare attualmente enormi limitazioni, superabili solo attraverso un diverso approccio nella produzione di chip, consistente in pratica nella sovrapposizione verticale di diversi strati collegati elettricamente attraverso speciali vias. Sul singolo strato, le network on chip sono state suggerite per ovviare le profonde limitazioni dovute allo scaling di strutture di comunicazione condivise. Questa tesi si colloca principalmente nel contesto delle nascenti piattaforme multicore ad alte prestazioni basate sulle 3D NoC, in cui la network on chip viene estesa nelle 3 direzioni. L’obiettivo di questo lavoro è quello di fornire una serie di strumenti e tecniche per poter costruire e aratterizzare una piattaforma tridimensionale, cosi come dimostrato nella realizzazione del testchip 3D NOC fabbricato presso la fonderia IMEC. Il primo contributo è costituito sia una accurata caratterizzazione delle interconnessioni verticali (TSVs) (ovvero delle speciali vias che attraversano l’intero substrato del die), sia dalla caratterizzazione dei router 3D (in cui una o più porte sono estese nella direzione verticale) ed infine dal setup di un design flow 3D utilizzando interamente CAD 2D. Questo primo step ci ha permesso di effettuare delle analisi dettagliate sia sul costo sia sulle varie implicazioni. Il secondo contributo è costituito dallo sviluppo di alcuni blocchi funzionali necessari per garantire il corretto funziomento della 3D NoC, in presenza sia di guasti nelle TSVs (fault tolerant links) che di deriva termica nei vari clock tree dei vari die (alberi di clock indipendenti). Questo secondo contributo è costituito dallo sviluppo delle seguenti soluzioni circuitali: 3D fault tolerant link, Look Up Table riconfigurabili e un sicnronizzatore mesocrono. Il primo è costituito fondamentalmente un bus verticale equipaggiato con delle TSV di riserva da utilizzare per rimpiazzare le vias guaste, più la logica di controllo per effettuare il test e la riconfigurazione. Il secondo è rappresentato da una Look Up Table riconfigurabile, ad alte prestazioni e dal costo contenuto, necesaria per bilanciare sia il traffico nella NoC che per bypassare link non riparabili. Infine la terza soluzione circuitale è rappresentata da un sincronizzatore mesocrono necessario per garantire la sincronizzazione nel trasferimento dati da un layer and un altro nelle 3D Noc. Il terzo contributo di questa tesi è dato dalla realizzazione di un interfaccia multicore per memorie 3D (stacked 3D DRAM) ad alte prestazioni, e dall’esplorazione architetturale dei benefici e del costo di questo nuovo sistema in cui il la memoria principale non è piu il collo di bottiglia dell’intero sistema. Il quarto ed ultimo contributo è rappresentato dalla realizzazione di un 3D NoC test chip presso la fonderia IMEC, e di un circuito full custom per la caratterizzazione della variability dei parametri RC delle interconnessioni verticali.

Lipophilic nucleosides: studies toward self-assembled functional materials

Molecular self-assembly takes advantage of supramolecular non-covalent interactions (ionic, hydrophobic, van der Waals, hydrogen and coordination bonds) for the construction of organized and tunable systems. In this field, lipophilic guanosines can represent powerful building blocks thanks to their aggregation proprieties in organic solvents, which can be controlled by addition or removal of cations. For example, potassium ion can template the formation of piled G-quartets structures, while in its absence ribbon-like G aggregates are generated in solution. In this thesis we explored the possibility of using guanosines as scaffolds to direct the construction of ordered and self-assembled architectures, one of the main goals of bottom-up approach in nanotechnology. In Chapter III we will describe Langmuir-Blodgett films obtained from guanosines and other lipophilic nucleosides, revealing the “special” behavior of guanine in comparison with the other nucleobases. In Chapter IV we will report the synthesis of several thiophene-functionalized guanosines and the studies towards their possible use in organic electronics: the pre-programmed organization of terthiophene residues in ribbon aggregates could allow charge conduction through π-π stacked oligothiophene functionalities. The construction and the behavior of some simple electronic nanodevices based on these organized thiopehene-guanosine hybrids has been explored.

Paleosol-based stratigraphy of late Quaternary deposits from the Po basin, between Bologna and the Po river (Northern Italy)

Stratigraphic studies carried out over the last decades in Italy and elsewhere testify a growing interest in Quaternary deposits and in the influence of climate change on their architecture. The subsurface of the Po Plain, in its topmost portion, is made up of alluvial deposits organized in depositional cycles at different scales. This PhD thesis provides millennial-scale stratigraphic reconstruction of the Late Pleistocene-Holocene deposits beneath the southern Po Plain, based on basin-scale correlation of laterally-extensive buried soil horizons. Far from the aim of characterizing palaeosols from a mineralogical and geochemical point of view, we focused on the physical and stratigraphic significance of these horizons. In the Bologna urban area, which hosts an abundance of stratigraphic data, the correlation between seventeen continuously-cored boreholes led to the identification of five vertically-stacked palaeosol-bounded sequences within the 14C time window. In a wide portion of the alluvial plain north of Bologna, far away from the Apenninic margin and from the Po River, where subsurface stratigraphic architecture is dominated by markedly lenticular sediment bodies, palaeosols revealed to be the only stratigraphic marker of remarkable lateral continuity. These horizons are characterized by peculiar resistance values, which make them easily identifiable via pocket penetration tests. Palaeosols reveal specific geometric relationships with the associated alluvial facies associations, allowing reliable estimates of soil development as a function of alluvial dynamics. With the aid of sixty new radiocarbon dates, a reliable age attribution and likely time intervals of exposure were assigned to each palaeosol. Vertically-stacked palaeosols delimitate short-term depositional cycles, likely related to the major episodes of climatic change of the last 40 ky. Through integration of stratigraphic data with 750 archaeological reports from the Bologna area, the impact of human settlements on depositional and pedogenic processes during the late Holocene was investigated.

Interfacial interactions, charge transport and growth phenomena in Organic Field Effect Transistors

Organic electronics is an emerging field with a vast number of applications having high potential for commercial success. Although an enormous progress has been made in this research area, many organic electronic applications such as organic opto-electronic devices, organic field effect transistors and organic bioelectronic devices still require further optimization to fulfill the requirements for successful commercialization. The main bottle neck that hinders large scale production of these devices is their performances and stability. The performance of the organic devices largely depends on the charge transport processes occurring at the interfaces of various material that it is composed of. As a result, the key ingredient needed for a successful improvement in the performance and stability of organic electronic devices is an in-depth knowledge of the interfacial interactions and the charge transport phenomena taking place at different interfaces. The aim of this thesis is to address the role of the various interfaces between different material in determining the charge transport properties of organic devices. In this framework, I chose an Organic Field Effect Transistor (OFET) as a model system to carry out this study as it An OFET offers various interfaces that can be investigated as it is made up of stacked layers of various material. In order to probe the intrinsic properties that governs the charge transport, we have to be able to carry out thorough investigation of the interactions taking place down at the accumulation layer thickness. However, since organic materials are highly instable in ambient conditions, it becomes quite impossible to investigate the intrinsic properties of the material without the influence of extrinsic factors like air, moisture and light. For this reason, I have employed a technique called the in situ real-time electrical characterization technique which enables electrical characterization of the OFET during the growth of the semiconductor.

Simulations for Gravitational Lensing of 21 cm Radiation at EoR and Post-EoR Redshifts

21 cm cosmology opens an observational window to previously unexplored cosmological epochs such as the Epoch of Reionization (EoR), the Cosmic Dawn and the Dark Ages using powerful radio interferometers such as the planned Square Kilometer Array (SKA). Among all the other applications which can potentially improve the understanding of standard cosmology, we study the promising opportunity given by measuring the weak gravitational lensing sourced by 21 cm radiation. We performed this study in two different cosmological epochs, at a typical EoR redshift and successively at a post-EoR redshift. We will show how the lensing signal can be reconstructed using a three dimensional optimal quadratic lensing estimator in Fourier space, using single frequency band or combining multiple frequency band measurements. To this purpose, we implemented a simulation pipeline capable of dealing with issues that can not be treated analytically. Considering the current SKA plans, we studied the performance of the quadratic estimator at typical EoR redshifts, for different survey strategies and comparing two thermal noise models for the SKA-Low array. The simulation we performed takes into account the beam of the telescope and the discreteness of visibility measurements. We found that an SKA-Low interferometer should obtain high-fidelity images of the underlying mass distribution in its phase 1 only if several bands are stacked together, covering a redshift range that goes from z=7 to z=11.5. The SKA-Low phase 2, modeled in order to improve the sensitivity of the instrument by almost an order of magnitude, should be capable of providing images with good quality even when the signal is detected within a single frequency band. Considering also the serious effect that foregrounds could have on this detections, we discussed the limits of these results and also the possibility provided by these models of measuring an accurate lensing power spectrum.