Static analysis of functionally graded cylindrical and conical shells or panels using the generalized unconstrained third order theory coupled with the stress recovery

A 2D Unconstrained Third Order Shear Deformation Theory (UTSDT) is presented for the evaluation of tangential and normal stresses in moderately thick functionally graded conical and cylindrical shells subjected to mechanical loadings. Several types of graded materials are investigated. The functionally graded material consists of ceramic and metallic constituents. A four parameter power law function is used. The UTSDT allows the presence of a finite transverse shear stress at the top and bottom surfaces of the graded shell. In addition, the initial curvature effect included in the formulation leads to the generalization of the present theory (GUTSDT). The Generalized Differential Quadrature (GDQ) method is used to discretize the derivatives in the governing equations, the external boundary conditions and the compatibility conditions. Transverse and normal stresses are also calculated by integrating the three dimensional equations of equilibrium in the thickness direction. In this way, the six components of the stress tensor at a point of the conical or cylindrical shell or panel can be given. The initial curvature effect and the role of the power law functions are shown for a wide range of functionally conical and cylindrical shells under various loading and boundary conditions. Finally, numerical examples of the available literature are worked out.

Studio del comportamento meccanico di smalti porcellanati per substrati metallici

Composite porcelain enamels are inorganic coatings for metallic components based on a special ceramic-vitreous matrix in which specific additives are randomly dispersed. The ceramic-vitreous matrix is made by a mixture of various raw materials and elements and in particular it is based on boron-silicate glass added with metal oxides(1) of titanium, zinc, tin, zirconia, alumina, ecc. These additions are often used to improve and enhance some important performances such as corrosion(2) and wear resistance, mechanical strength, fracture toughness and also aesthetic functions. The coating process, called enamelling, depends on the nature of the surface, but also on the kind of the used porcelain enamel. For metal sheets coatings two industrial processes are actually used: one based on a wet porcelain enamel and another based on a dry-silicone porcelain enamel. During the firing process, that is performed at about 870°C in the case of a steel substrate, the enamel raw material melts and interacts with the metal substrate so enabling the formation of a continuous varying structure. The interface domain between the substrate and the external layer is made of a complex material system where the ceramic vitreous and the metal constituents are mixed. In particular four main regions can be identified, (i) the pure metal region, (ii) the region where the metal constituents are dominant compared with the ceramic vitreous components, (iii) the region where the ceramic vitreous constituents are dominant compared with the metal ones, and the fourth region (iv) composed by the pure ceramic vitreous material. It has also to be noticed the presence of metallic dendrites that hinder the substrate and the external layer passing through the interphase region. Each region of the final composite structure plays a specific role: the metal substrate has mainly the structural function, the interphase region and the embedded dendrites guarantee the adhesion of the external vitreous layer to the substrate and the external vitreous layer is characterized by an high tribological, corrosion and thermal shock resistance. Such material, due to its internal composition, functionalization and architecture can be considered as a functionally graded composite material. The knowledge of the mechanical, tribological and chemical behavior of such composites is not well established and the research is still in progress. In particular the mechanical performances data about the composite coating are not jet established. In the present work the Residual Stresses, the Young modulus and the First Crack Failure of the composite porcelain enamel coating are studied. Due to the differences of the porcelain composite enamel and steel thermal properties the enamelled steel sheets have residual stresses: compressive residual stress acts on the coating and tensile residual stress acts on the steel sheet. The residual stresses estimation has been performed by measuring the curvature of rectangular one-side coated specimens. The Young modulus and the First Crack Failure (FCF) of the coating have been estimated by four point bending tests (3-7) monitored by means of the Acoustic Emission (AE) technique(5,6). In particular the AE information has been used to identify, during the bending tests, the displacement domain over which no coating failure occurs (Free Failure Zone, FFZ). In the FFZ domain, the Young modulus has been estimated according to ASTM D6272-02. The FCF has been calculated as the ratio between the displacement at the first crack of the coating and the coating thickness on the cracked side. The mechanical performances of the tested coated specimens have also been related and discussed to respective microstructure and surface characteristics by double entry charts.

Multilaminati piezoelettrici a gradiente funzionale

Aim of this thesis was the production of porosity-graded piezoelectric ceramics for ultrasonic applications by tape casting and screen printing. The study and optimization of each single step of the tape casting process allowed to produce flat and crack-free multilayers of Pb0.988(Zr0.52Ti0.48)0.976Nb0.024O3 (PZTN) of uniform and graded porosity. The multilayers of thickness ranging between 400 and 800 µm were produced stacking optimized green layers with different amount of pore former. The functionally graded materials showed porosity ranging between 10 and 30% with piezoelectric properties suitable for the specific ultrasonic applications. Screen printing inks of PZTN for deposition onto four different substrates were studied and optimized. Thick films with thickness ranging between 4 and 20 µm were produced tailoring the screen printing parameters and number of depositions.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.