Un concetto innovativo di limitatore di corrente di guasto superconduttivo

The thesis topic concerns the limitation of fault current high temperature superconducting (HTS), reported in scientific literature by the acronym HTSFCL (High Temperature Superconducting Fault Current Limiter) or more commonly with SFCL. These devices, at least in their ideal concept, turn on limiting short-circuit current only when the event of failure occurs, and are transparent to the network during normal operating conditions. The thesis is therefore focused on the study of diff�erent types of SFCL and results in the production of a new and original concept of superconducting limiter, called "DC Resistive SFCL". It has designed and patented in the Department of Electrical Engineering University of Bologna. The author and ing. Antonio Morandi (tutor) are the inventors. The objective of the thesis is therefore to propose a type of SFCL which may have the potential to be a viable economic solution as well as technique. The innovative concept of DC Resistive SFCL device, in fact, provides a DC operating conditions for the used superconducting (SC). It allows the use of cryogen-free solutions for cooling system and the exploitation of cheap SC materials (MgB2), both of reality are already commercially existing and indeed precluded by the types of SFCL which provides an AC operating conditions for the used SC material.

Model predictive control in thermal management of multiprocessor systems-on-chip

MultiProcessor Systems-on-Chip (MPSoC) are the core of nowadays and next generation computing platforms. Their relevance in the global market continuously increase, occupying an important role both in everydaylife products (e.g. smartphones, tablets, laptops, cars) and in strategical market sectors as aviation, defense, robotics, medicine. Despite of the incredible performance improvements in the recent years processors manufacturers have had to deal with issues, commonly called “Walls”, that have hindered the processors development. After the famous “Power Wall”, that limited the maximum frequency of a single core and marked the birth of the modern multiprocessors system-on-chip, the “Thermal Wall” and the “Utilization Wall” are the actual key limiter for performance improvements. The former concerns the damaging effects of the high temperature on the chip caused by the large power densities dissipation, whereas the second refers to the impossibility of fully exploiting the computing power of the processor due to the limitations on power and temperature budgets. In this thesis we faced these challenges by developing efficient and reliable solutions able to maximize performance while limiting the maximum temperature below a fixed critical threshold and saving energy. This has been possible by exploiting the Model Predictive Controller (MPC) paradigm that solves an optimization problem subject to constraints in order to find the optimal control decisions for the future interval. A fully-distributedMPC-based thermal controller with a far lower complexity respect to a centralized one has been developed. The control feasibility and interesting properties for the simplification of the control design has been proved by studying a partial differential equation thermal model. Finally, the controller has been efficiently included in more complex control schemes able to minimize energy consumption and deal with mixed-criticalities tasks