Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS

Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.

Analysis of Copy Number Variants identifies new candidate genes for Autism Spectrum Disorder and Intellectual Disability

Autism spectrum disorder (ASD) and Intellectual Disability (ID) are complex neuropsychiatric disorders characterized by extensive clinical and genetic heterogeneity and with overlapping risk factors. The aim of my project was to further investigate the role of Copy Numbers Variants (CNVs), identified through genome-wide studies performed by the Autism Geome Project (AGP) and the CHERISH consortium in large cohorts of ASD and ID cases, respectively. Specifically, I focused on four rare genic CNVs, selected on the basis of their impact on interesting ASD/ID candidate genes: a) a compound heterozygous deletion involving CTNNA3, predicted to cause the lack of functional protein; b) a 15q13.3 duplication containing CHRNA7; c) a 2q31.1 microdeletion encompassing KLHL23, SSB and METTL5; d) Lastly, I investigated the putative imprinting regulation of the CADPS2 gene, disrupted by a maternal deletion in two siblings with ASD and ID. This study provides further evidence for the role of CTNNA3, CHRNA7, KLHL23 and CADPS2 as ASD and/or ID susceptibility genes, and highlights that rare genetic variation contributes to disease risk in different ways: some rare mutations, such as those impacting CTNNA3, act in a recessive mode of inheritance, while other CNVs, such as those occurring in the 15q13.3 region, are implicated in multiple developmental and/or neurological disorders possibly interacting with other susceptibility variants elsewhere in the genome. On the other hand, the discovery of a tissue-specific monoallelic expression for the CADPS2 gene, implicates the involvement of epigenetic regulatory mechanisms as risk factors conferring susceptibility to ASD/ID.