Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures

The scale down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as they struggle to sustain the increasing tight bandwidth and latency constraints that these systems demand. The most promising solution for the future chip interconnects are the Networks on Chip (NoC). NoCs are network composed by routers and channels used to inter- connect the different components installed on the single microchip. Examples of advanced processors based on NoC interconnects are the IBM Cell processor, composed by eight CPUs that is installed on the Sony Playstation III and the Intel Teraflops pro ject composed by 80 independent (simple) microprocessors. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider and more heterogeneous world of Systems on Chip (SoC). SoC comprehend all the electronic devices that surround us such as cell-phones, smart-phones, house embedded systems, automotive systems, set-top boxes etc... SoC manufacturers such as ST Microelectronics , Samsung, Philips and also Universities such as Bologna University, M.I.T., Berkeley and more are all proposing proprietary frameworks based on NoC interconnects. These frameworks help engineers in the switch of design methodology and speed up the development of new NoC-based systems on chip. In this Thesis we propose an introduction of CMP and SoC interconnection networks. Then focusing on SoC systems we propose: • a detailed analysis based on simulation of the Spidergon NoC, a ST Microelectronics solution for SoC interconnects. The Spidergon NoC differs from many classical solutions inherited from the parallel computing world. Here we propose a detailed analysis of this NoC topology and routing algorithms. Furthermore we propose aEqualized a new routing algorithm designed to optimize the use of the resources of the network while also increasing its performance; • a methodology flow based on modified publicly available tools that combined can be used to design, model and analyze any kind of System on Chip; • a detailed analysis of a ST Microelectronics-proprietary transport-level protocol that the author of this Thesis helped developing; • a simulation-based comprehensive comparison of different network interface designs proposed by the author and the researchers at AST lab, in order to integrate shared-memory and message-passing based components on a single System on Chip; • a powerful and flexible solution to address the time closure exception issue in the design of synchronous Networks on Chip. Our solution is based on relay stations repeaters and allows to reduce the power and area demands of NoC interconnects while also reducing its buffer needs; • a solution to simplify the design of the NoC by also increasing their performance and reducing their power and area consumption. We propose to replace complex and slow virtual channel-based routers with multiple and flexible small Multi Plane ones. This solution allows us to reduce the area and power dissipation of any NoC while also increasing its performance especially when the resources are reduced. This Thesis has been written in collaboration with the Advanced System Technology laboratory in Grenoble France, and the Computer Science Department at Columbia University in the city of New York.

Vulnerability and robustness indices against blackouts in power grids

In this dissertation some novel indices for vulnerability and robustness assessment of power grids are presented. Such indices are mainly defined from the structure of transmission power grids, and with the aim of Blackout (BO) prevention and mitigation. Numerical experiments showing how they could be used alone or in coordination with pre-existing ones to reduce the effects of BOs are discussed. These indices are introduced inside 3 different sujects: The first subject is for taking a look into economical aspects of grids’ operation and their effects in BO propagation. Basically, simulations support that: the determination to operate the grid in the most profitable way could produce an increase in the size or frequency of BOs. Conversely, some uneconomical ways of supplying energy are shown to be less affected by BO phenomena. In the second subject new topological indices are devised to address the question of "which are the best buses to place distributed generation?". The combined use of two indices, is shown as a promising alternative for extracting grid’s significant features regarding robustness against BOs and distributed generation. For this purpose, a new index based on outage shift factors is used along with a previously defined electric centrality index. The third subject is on Static Robustness Analysis of electric networks, from a purely structural point of view. A pair of existing topological indices, (namely degree index and clustering coefficient), are combined to show how degradation of the network structure can be accelerated. Blackout simulations were carried out using the DC Power Flow Method and models of transmission networks from the USA and Europe.