Performance evaluation on electronic control systemsfor field sprayers using programmable logic controllers

The aim of this study was to develop a laboratory method for time response evaluation on electronically controlled spray equipment using Programmable Logic Controllers (PLCs). For that purpose, a PLC controlled digital drive inverter was set up to drive an asynchronous electric motor linked to a centrifugal pump on a experimental sprayer equipped with electronic flow control. The PLC was operated via RS232 serial communication from a PC computer. A user program was written to control de motor by adjusting the following system variables, all related to the motor speed: time stopped; ramp up and ramp down times, time running at a given constant speed and ramp down time to stop the motor. This set up was used in conjunction with a data acquisition system to perform laboratory tests with an electronically controlled sprayer. Time response for pressure stabilization was measured while changing the pump speed by +/-20%. The results showed that for a 0.2 s ramp time increasing the motor speed, as an example, an AgLogix Flow Control system (Midwest Technologies Inc.) took 22 s in average to readjust the pressure. When decreasing the motor speed, this time response was down to 8 s. General results also showed that this kind of methodology could make easier the definition of standards for tests on electronically controlled application equipment.

A current-mode based Field-Programmable Analog Array for signal processing applications

This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.

A novel programmable PFC based hybrid rectifier for ultra clean power application

A novel hybrid high power rectifier capable to achieve unity power factor is proposed in this paper. Single-phase SEPIC rectifiers are associated in parallel with each leg of three-phase 6-pulse diode rectifier resulting in a programmable input current waveform structure. In this paper it is described the principles of operation of the proposed converter with detailed simulation and experimental results. For a total harmonic distortion of the input line current (THDI) less than 2% the rated power of the SEPIC rectifiers is 33%. Therefore, power rating of the SEPIC parallel converters is a fraction of the output power, on the range of 20% to 33% of the nominal output power, making the proposed solution economically viable for high power installations, with fast pay back of the investment. Moreover, retrofits to existing installations are also possible with this proposed topology, since the parallel path can be easily controlled by integration with the already existing de-link. Experimental results are presented for a 3 kW implemented prototype, in order to verify the developed analysis.

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

A true programmable HPF hybrid three-phase rectifier

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. The proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. Finally, the proposed control strategy is verified through experimental results from an implemented prototype. ©2008 IEEE.

Hybrid three-phase HPF rectifier with programmable input current THD, using FPGA device and VHDL language

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. Finally, the proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. The proposed strategy is verified by experiments. © 2008 IEEE.

Controle digital através de dispositivo FPGA aplicado a um retificador trifásico híbrido operando com modulação por histerese variável

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A novel HPF voltage source rectifier for variable speed refrigeration systems

A novel single-phase voltage source rectifier capable to achieve High-Power-Factor (HPF) for variable speed refrigeration system application, is proposed in this paper. The proposed system is composed by a single-phase high-power-factor boost rectifier, with two cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the EEC61000-3-2 standards. The digital controller for the output stage has been developed using a conventional voltage-frequency control (scalar V/f control), and a simplified stator oriented Vector control, in order to verify the feasibility and performance of the proposed digital controls for continuous temperature control applied at a refrigerator prototype.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests. (c) 2008 Elsevier B.V. All rights reserved.

Open and Standardized Resources for Smart Transducer Networking

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Design of a reconfigurable pseudorandom number generator for use in intelligent systems

This paper deals with the design of a network-on-chip reconfigurable pseudorandom number generation unit that can map and execute meta-heuristic algorithms in hardware. The unit can be configured to implement one of the following five linear generator algorithms: a multiplicative congruential, a mixed congruential, a standard multiple recursive, a mixed multiple recursive, and a multiply-with-carry. The generation unit can be used both as a pseudorandom and a message passing-based server, which is able to produce pseudorandom numbers on demand, sending them to the network-on-chip blocks that originate the service request. The generator architecture has been mapped to a field programmable gate array, and showed that millions of numbers in 32-, 64-, 96-, or 128-bit formats can be produced in tens of milliseconds. (C) 2011 Elsevier B.V. All rights reserved.

A multi-cell variable frequency interleaved ZCS boost rectifier digitally controlled by FPGA

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by Field Programmable Gate Array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-vohage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a preregulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

Evolvable hardware applied to voice recognition

This paper presents some results of the application on Evolvable Hardware (EHW) in the area of voice recognition. Evolvable Hardware is able to change inner connections, using genetic learning techniques, adapting its own functionality to external condition changing. This technique became feasible by the improvement of the Programmable Logic Devices. Nowadays, it is possible to have, in a single device, the ability to change, on-line and in real-time, part of its own circuit. This work proposes a reconfigurable architecture of a system that is able to receive voice commands to execute special tasks as, to help handicapped persons in their daily home routines. The idea is to collect several voice samples, process them through algorithms based on Mel - Ceptrais theory to obtain their numerical coefficients for each sample, which, compose the universe of search used by genetic algorithm. The voice patterns considered, are limited to seven sustained Portuguese vowel phonemes (a, eh, e, i, oh, o, u).

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.