4 resultados para Decoder

em Repositório Institucional UNESP - Universidade Estadual Paulista "Julio de Mesquita Filho"


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A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

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Pós-graduação em Televisão Digital: Informação e Conhecimento - FAAC

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This study establishes that for a given binary BCH code C0 n of length n generated by a polynomial g(x) ∈ F2[x] of degree r there exists a family of binary cyclic codes {Cm 2m−1(n+1)n}m≥1 such that for each m ≥ 1, the binary cyclic code Cm 2m−1(n+1)n has length 2m−1(n + 1)n and is generated by a generalized polynomial g(x 1 2m ) ∈ F2[x, 1 2m Z≥0] of degree 2mr. Furthermore, C0 n is embedded in Cm 2m−1(n+1)n and Cm 2m−1(n+1)n is embedded in Cm+1 2m(n+1)n for each m ≥ 1. By a newly proposed algorithm, codewords of the binary BCH code C0 n can be transmitted with high code rate and decoded by the decoder of any member of the family {Cm 2m−1(n+1)n}m≥1 of binary cyclic codes, having the same code rate.