51 resultados para LEAKAGE CURRENT
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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The ferroelectric properties and leakage current mechanisms of preferred oriented Bi3.25La0.75 Ti3O12 (BLT) thin films deposited on La0.5Sr0.5CoO3 (LSCO) by the polymeric precursor method were investigated. Atomic force microscopy indicates that the deposited films exhibit a dense microstructure with a rather smooth surface morphology. The improved ferroelectric and leakage current characteristics can be ascribed to the plate-like grains of the BLT films. © 2006 Trans Tech Publications, Switzerland.
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
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This article compares the efficiency of induced polarization (IP) and resistivity in characterizing a contamination plume due to landfill leakage in a typical tropical environment. The resistivity survey revealed denser electrical current flow that induced lower resistivity values due to the high ionic content. The increased ionic concentration diminished the distance of the ionic charges close to the membrane, causing a decrease in the IP phenomena. In addition, the self-potential (SP) method was used to characterize the preferential flow direction of the area. The SP method proved to be effective at determining the flow direction; it is also fast and economical. In this study, the resistivity results were better correlated with the presence of contamination (lower resistivity) than the IP (lower chargeability) data.
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An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.