70 resultados para intel processor


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Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads. © 2012 IEEE.

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Software transaction memory (STM) systems have been used as an approach to improve performance, by allowing the concurrent execution of atomic blocks. However, under high-contention workloads, STM-based systems can considerably degrade performance, as transaction conflict rate increases. Contention management policies have been used as a way to select which transaction to abort when a conflict occurs. In general, contention managers are not capable of avoiding conflicts, as they can only select which transaction to abort and the moment it should restart. Since contention managers act only after a conflict is detected, it becomes harder to effectively increase transaction throughput. More proactive approaches have emerged, aiming at predicting when a transaction is likely to abort, postponing its execution. Nevertheless, most of the proposed proactive techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction to run. This article proposes LUTS, a lightweight user-level transaction scheduler. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. We discuss LUTS design and propose a dynamic conflict-avoidance heuristic built around its scheduling capabilities. Experimental results, conducted with the STAMP and STMBench7 benchmark suites, running on TinySTM and SwissTM, show how our conflict-avoidance heuristic can effectively improve STM performance on high contention applications. © 2012 Springer Science+Business Media, LLC.

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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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Pós-graduação em Agronomia (Energia na Agricultura) - FCA

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)