35 resultados para Hardware description language
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
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Pós-graduação em Ciência da Computação - IBILCE
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
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Pós-graduação em Engenharia Elétrica - FEIS
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Pós-graduação em Engenharia Elétrica - FEIS
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In many movies of scientific fiction, machines were capable of speaking with humans. However mankind is still far away of getting those types of machines, like the famous character C3PO of Star Wars. During the last six decades the automatic speech recognition systems have been the target of many studies. Throughout these years many technics were developed to be used in applications of both software and hardware. There are many types of automatic speech recognition system, among which the one used in this work were the isolated word and independent of the speaker system, using Hidden Markov Models as the recognition system. The goals of this work is to project and synthesize the first two steps of the speech recognition system, the steps are: the speech signal acquisition and the pre-processing of the signal. Both steps were developed in a reprogrammable component named FPGA, using the VHDL hardware description language, owing to the high performance of this component and the flexibility of the language. In this work it is presented all the theory of digital signal processing, as Fast Fourier Transforms and digital filters and also all the theory of speech recognition using Hidden Markov Models and LPC processor. It is also presented all the results obtained for each one of the blocks synthesized e verified in hardware
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Pós-graduação em Engenharia Elétrica - FEIS
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This paper describes the first polytomous computerised identification key within the family Phytoseiidae. It applies to the females of the world species of the subgenus Typhlodromus (Anthoseius) de Leon. This group is one of the largest within the family Phytoseiidae and the sub-family Typhlodrominae, with nearly 350 species currently recognised worldwide. No identification tool of these species exists at the world level, which makes their identification very difficult and unsecure. Thirty five characters were used to characterise each of the 343 species. Among these characters, 14 are discrete and 21 are continuous. The polytomous key was constructed using the free software DELTA 1.04 (DEscription Language for TAxonomy) and is freely available at the web site: http://www1.montpellier.inra.fr/CBGP/phytoseiidae/anthoseiuskeypresentation.html. We hope that this work will open new perspectives for the identification of species of other genera (especially the largest ones, e.g. Neoseiulus, Euseius, Amblyseius) which contains more than 150 species and for which no key presently exists. We also expect that the present work will make the identification of the world species of Typhlodromus (Anthoseius) easier and more secure. Finally, we expect a contribution from the whole Phytoseiidae scientist community to improve subsequent versions of the key.
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This paper presents a tool box developed to read files describing a SIMULINK® model and translates it into a structural VHDL-AMS description. In translation process, all files and directory structures to simulate the translated model on SystemVision™ environment is generate. The tool box named MS2SV was tested by three models of commercially available digital-to-analogue converters. All models use the R2R ladder network to conversion, but the functionality of these three components is different. The methodology of conversion of the model is presents together with sort theory about R-2R ladder network. In the evaluation of the translated models, we used a sine waveform input signal and the waveform generated by D/A conversion process was compared by FFT analysis. The results show the viability of this type of approach. This work considers some of challenges set by the electronic industry for the further development of simulation methodologies and tools in the field of mixed-signal technology. © 2007 IEEE.
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The constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC.
Improvement and evaluation of the MS2SV for mixed systems design described in abstraction high level
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This paper presents an important improvement of the MS2SV tool. The MS2SV performs the translation of mixed systems developed in MATLAB / Simulink for a structural or behavioral description in VHDL-AMS. Previously, the MS2SV translated only models of the LIB MS2SV library. This improvement allows designer to create your own library to translation. As case study was used a rudder controller employed in an unmanned aerial vehicle. For comparison with the original model the VHDL-AMS code obtained by the translation was simulated in SystemVision environment. The results proved the efficiency of the tool using the translation improvement proposed in this paper.
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This paper presents a distribution feeder simulation using VHDL-AMS, considering the standard IEEE 13 node test feeder admitted as an example. In an electronic spreadsheet all calculations are performed in order to develop the modeling in VHDL-AMS. The simulation results are compared in relation to the results from the well knowing MatLab/Simulink environment, in order to verify the feasibility of the VHDL-AMS modeling for a standard electrical distribution feeder, using the software SystemVision™. This paper aims to present the first major developments for a future Real-Time Digital Simulator applied to Electrical Power Distribution Systems. © 2012 IEEE.
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)