On designing linearly-tunable ultra-low voltage CMOS gm-C filters

A linearly-tunable ULV transconductor featuring excellent stability of the processed signal common-mode voltage upon tuning, critical for very-low voltage applications, is presented. Its employment to the synthesis of CMOS gm-C high-frequency and voiceband filters is discussed. SPICE data describe the filter characteristics. For a 1.3 V-supply, their nominal passband frequencies are 1.0 MHz and 3.78 KHz, respectively, with tuning rates of 12.52 KHz/mV and 0.16 KHz/m V, input-referred noise spectral density of 1.3 μV/Hz1/2 and 5.0μV/Hz1/2 and standby consumption of 0.87 mW and 11.8 μW. Large-signal distortion given by THD = 1% corresponds to a differential output-swing of 360 mVpp and 480 mVpp, respectively. Common-mode voltage deviation is less than 4 mV over tuning interval.

A high speed 3.3V current mode CMOS comparators with 10-b resolution

This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, ±0.5uA resolution and has fast response. This circuit was implemented with 0.8μm CMOS n-well process with area of 120μm × 105μm and operates with 3.3V(±1.65V).

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift

A new topology for a LVLP variable-gain CMOS amplifier is presented. Input- and load-stage are built around triode-transconductors so that voltage-gain is fully defined by a linear relationship involving only device-geometries and biases. Excellent gain-accuracy, temperature-insensitivity; and wide range of programmability, are thus achieved. Moreover, adaptative biasing improves the common-mode voltage stability upon gain-adjusting. As an example, a 0-40dB programmablegain audio-amplifier is designed. Its performance is supported by a range of simulations. For VDD=1.8V and 20dB-nominal gain, one has Av=19.97dB, f3db=770KHz and quiescent dissipation of 378μW. Over temperatures from -25°C to 125°C, the 0. ldB-bandwidth is 52KHz. Dynamic-range is optimized to 57.2dB and 42.6dB for gains of 20dB and 40dB, respectively. THD figures correspond to -60.6dB@Vout= 1Vpp and -79.7dB@Vout= 0.5 Vpp. A nearly constant bandwidth for different gains is also attained.

CMOS-based active pixel for low-light-level detection: Analysis and measurements

An analysis of the active pixel sensor (APS), considering the doping profiles of the photodiode in an APS fabricated in a 0.18 μm standard CMOS technology, is presented. A simple and accurate model for the junction capacitance of the photodiode is proposed. An analytic expression for the output voltage of the APS obtained with this capacitance model is in good agreement with measurements and is more accurate than the models used previously. A different mode of operation for the APS based on the dc level of the output is suggested. This new mode has better low-light-level sensitivity than the conventional APS operating mode, and it has a slower temporal response to the change of the incident light power. At 1μW/cm2 and lower levels of light, the measured signal-to-noise ratio (SNR) of this new mode is more than 10 dB higher than the SNR of previously reported APS circuits. Also, with an output SNR of about 10 dB, the proposed dc level is capable of detecting light powers as low as 20 nW/cm2, which is about 30 times lower than the light power detected in recent reports by other groups. © 2007 IEEE.

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35νm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator and a D flip-flop having 16% fill-factor and 30νmx26νm dimensions. The multisampling architecture requires only a 1 bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The advantage is that the number of transistors in the pixel is low, saving area and providing higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operation in video mode with 10 bits. Also, we present analysis for the impact of comparator offset voltage in the fixed pattern noise. Copyright 2007 ACM.

Design of a CMOS voltage reference using current-model approach

A voltage reference with low sensibility to temperature and power-supply that can generate flexible reference values (from milivolts to several volts) is proposed. Designed for AMS 0.35μm CMOS process, the circuit provides a stable output voltage working in the temperature range of -40-150°C. The proposed reference provides a nominal output voltage of 1.358V with a power-supply of 3.3V. © 2011 IEEE.

Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Proposta de implementação de redes de base radial em tecnologias CMOS e BiCMOS

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Desenvolvimento e implementação de um sintetizador de frequência CMOS utilizando sistema digital

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Projeto de um Multiplicador Divisor Anal´ogico em tecnologia CMOS para uso em controlador fuzzy tipo-2 intervalar

The main objective of the presented study is the design of a analog multiplier-divider as integrant part of the type-reducer circuit of type-2 fuzzy controller chip. The proposed circuit is a multiplier/divider which operates in current mode, in the CMOS technology with a supply voltage of 1.8 V.The circuit simulation was performed in PSPICE software with simulation model provided by AMS (Austria Mikro Systems International) in CMOS technology 0.35μm

Al2O3 obtained through resistive evaporation for use as insulating layer in transparent field effect transistor

Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation achieved by annealing in appropriate atmosphere (air or O-2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550 degrees C is responsible for fair oxidation. Results of surface electrical resistivity, Raman and infrared spectroscopies are in good agreement with this finding. X-ray and Raman data also suggest the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. The main goal in this work is the deposition of alumina on top of SnO2 to build a transparent field-effect transistor. Some microscopy results of the assembled SnO2/Al2O3 heterostructure are also shown.

Al2O3 Obtained through resistive evaporation for use as insulating layer in transparent field effect transistor

Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation achieved by annealing in appropriate atmosphere (air or O2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550°C is responsible for fair oxidation. Results of surface electrical resistivity, Raman and infrared spectroscopies are in good agreement with this finding. X-ray and Raman data also suggest the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. The main goal in this work is the deposition of alumina on top of SnO2 to build a transparent field-effect transistor. Some microscopy results of the assembled SnO2/Al2O3 heterostructure are also shown.

Conversor analógico digital de 10 bits utilizando arquitetura pipeline e tecnologia CMOS

Pós-graduação em Engenharia Elétrica - FEIS